From a9d55b04c0ec3b2842f36f5771211704dc1255b1 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 25 Sep 2019 14:07:28 +0200 Subject: [PATCH] boards/netv2: switch to MVP, add spiflashx4 and hdmi in/out --- litex/boards/platforms/netv2.py | 100 +++++++++++++++++++++++++------- litex/boards/targets/netv2.py | 2 + 2 files changed, 81 insertions(+), 21 deletions(-) diff --git a/litex/boards/platforms/netv2.py b/litex/boards/platforms/netv2.py index 9a07b4fd..786dee3e 100644 --- a/litex/boards/platforms/netv2.py +++ b/litex/boards/platforms/netv2.py @@ -18,7 +18,7 @@ _io = [ ("user_led", 4, Pins("R19"), IOStandard("LVCMOS33")), ("user_led", 5, Pins("M16"), IOStandard("LVCMOS33")), - # flash + # spiflash ("flash", 0, Subsignal("cs_n", Pins("T19")), Subsignal("mosi", Pins("P22")), @@ -28,6 +28,13 @@ _io = [ IOStandard("LVCMOS33") ), + # spiflash4x + ("spiflash4x", 0, + Subsignal("cs_n", Pins("T19")), + Subsignal("dq", Pins("P22 R22 P21 R21")), + IOStandard("LVCMOS33") + ), + # serial ("serial", 0, Subsignal("tx", Pins("E14")), @@ -39,28 +46,28 @@ _io = [ ("ddram", 0, Subsignal("a", Pins( "U6 V4 W5 V5 AA1 Y2 AB1 AB3", - "AB2 Y3 W6 Y1 V2 AA3" - ), - IOStandard("SSTL15")), - Subsignal("ba", Pins("U5 W4 V7"), IOStandard("SSTL15")), - Subsignal("ras_n", Pins("Y9"), IOStandard("SSTL15")), - Subsignal("cas_n", Pins("Y7"), IOStandard("SSTL15")), - Subsignal("we_n", Pins("V8"), IOStandard("SSTL15")), - Subsignal("dm", Pins("M5 L3"), IOStandard("SSTL15")), + "AB2 Y3 W6 Y1 V2 AA3"), + IOStandard("SSTL15_R")), + Subsignal("ba", Pins("U5 W4 V7"), IOStandard("SSTL15_R")), + Subsignal("ras_n", Pins("Y9"), IOStandard("SSTL15_R")), + Subsignal("cas_n", Pins("Y7"), IOStandard("SSTL15_R")), + Subsignal("we_n", Pins("V8"), IOStandard("SSTL15_R")), + Subsignal("dm", Pins("G1 H4 M5 L3"), IOStandard("SSTL15_R")), Subsignal("dq", Pins( - "N2 M6 P1 N5 P2 N4 R1 P6 " - "K3 M2 K4 M3 J6 L5 J4 K6 " - ), - IOStandard("SSTL15"), - Misc("IN_TERM=UNTUNED_SPLIT_50")), - Subsignal("dqs_p", Pins("P5 M1"), IOStandard("DIFF_SSTL15")), - Subsignal("dqs_n", Pins("P4 L1"), IOStandard("DIFF_SSTL15")), - Subsignal("clk_p", Pins("R3"), IOStandard("DIFF_SSTL15")), - Subsignal("clk_n", Pins("R2"), IOStandard("DIFF_SSTL15")), - Subsignal("cke", Pins("Y8"), IOStandard("SSTL15")), - Subsignal("odt", Pins("W9"), IOStandard("SSTL15")), + "C2 F1 B1 F3 A1 D2 B2 E2", + "J5 H3 K1 H2 J1 G2 H5 G3", + "N2 M6 P1 N5 P2 N4 R1 P6", + "K3 M2 K4 M3 J6 L5 J4 K6"), + IOStandard("SSTL15_R"), + Misc("IN_TERM=UNTUNED_SPLIT_40")), + Subsignal("dqs_p", Pins("E1 K2 P5 M1"), IOStandard("DIFF_SSTL15_R")), + Subsignal("dqs_n", Pins("D1 J2 P4 L1"), IOStandard("DIFF_SSTL15_R")), + Subsignal("clk_p", Pins("R3"), IOStandard("DIFF_SSTL15_R")), + Subsignal("clk_n", Pins("R2"), IOStandard("DIFF_SSTL15_R")), + Subsignal("cke", Pins("Y8"), IOStandard("SSTL15_R")), + Subsignal("odt", Pins("W9"), IOStandard("SSTL15_R")), Subsignal("reset_n", Pins("AB5"), IOStandard("LVCMOS15")), - Subsignal("cs_n", Pins("V9"), IOStandard("SSTL15")), + Subsignal("cs_n", Pins("V9"), IOStandard("SSTL15_R")), Misc("SLEW=FAST"), ), @@ -90,6 +97,57 @@ _io = [ Subsignal("clk", Pins("K18")), IOStandard("LVCMOS33"), Misc("SLEW=FAST") ), + + # hdmi in + ("hdmi_in", 0, + Subsignal("clk_p", Pins("L19"), IOStandard("TMDS_33"), Inverted()), + Subsignal("clk_n", Pins("L20"), IOStandard("TMDS_33"), Inverted()), + Subsignal("data0_p", Pins("K21"), IOStandard("TMDS_33"), Inverted()), + Subsignal("data0_n", Pins("K22"), IOStandard("TMDS_33"), Inverted()), + Subsignal("data1_p", Pins("J20"), IOStandard("TMDS_33"), Inverted()), + Subsignal("data1_n", Pins("J21"), IOStandard("TMDS_33"), Inverted()), + Subsignal("data2_p", Pins("J22"), IOStandard("TMDS_33"), Inverted()), + Subsignal("data2_n", Pins("H22"), IOStandard("TMDS_33"), Inverted()), + Subsignal("scl", Pins("T18"), IOStandard("LVCMOS33")), + Subsignal("sda", Pins("V18"), IOStandard("LVCMOS33")), + ), + + ("hdmi_in", 1, + Subsignal("clk_p", Pins("Y18"), IOStandard("TMDS_33"), Inverted()), + Subsignal("clk_n", Pins("Y19"), IOStandard("TMDS_33"), Inverted()), + Subsignal("data0_p", Pins("AA18"), IOStandard("TMDS_33")), + Subsignal("data0_n", Pins("AB18"), IOStandard("TMDS_33")), + Subsignal("data1_p", Pins("AA19"), IOStandard("TMDS_33"), Inverted()), + Subsignal("data1_n", Pins("AB20"), IOStandard("TMDS_33"), Inverted()), + Subsignal("data2_p", Pins("AB21"), IOStandard("TMDS_33"), Inverted()), + Subsignal("data2_n", Pins("AB22"), IOStandard("TMDS_33"), Inverted()), + Subsignal("scl", Pins("W17"), IOStandard("LVCMOS33"), Inverted()), + Subsignal("sda", Pins("R17"), IOStandard("LVCMOS33")), + ), + + # hdmi out + ("hdmi_out", 0, + Subsignal("clk_p", Pins("W19"), Inverted(), IOStandard("TMDS_33")), + Subsignal("clk_n", Pins("W20"), Inverted(), IOStandard("TMDS_33")), + Subsignal("data0_p", Pins("W21"), IOStandard("TMDS_33")), + Subsignal("data0_n", Pins("W22"), IOStandard("TMDS_33")), + Subsignal("data1_p", Pins("U20"), IOStandard("TMDS_33")), + Subsignal("data1_n", Pins("V20"), IOStandard("TMDS_33")), + Subsignal("data2_p", Pins("T21"), IOStandard("TMDS_33")), + Subsignal("data2_n", Pins("U21"), IOStandard("TMDS_33")) + ), + + ("hdmi_out", 1, + Subsignal("clk_p", Pins("G21"), IOStandard("TMDS_33"), Inverted()), + Subsignal("clk_n", Pins("G22"), IOStandard("TMDS_33"), Inverted()), + Subsignal("data0_p", Pins("E22"), IOStandard("TMDS_33"), Inverted()), + Subsignal("data0_n", Pins("D22"), IOStandard("TMDS_33"), Inverted()), + Subsignal("data1_p", Pins("C22"), IOStandard("TMDS_33"), Inverted()), + Subsignal("data1_n", Pins("B22"), IOStandard("TMDS_33"), Inverted()), + Subsignal("data2_p", Pins("B21"), IOStandard("TMDS_33"), Inverted()), + Subsignal("data2_n", Pins("A21"), IOStandard("TMDS_33"), Inverted()), + ), + ] # Platform ----------------------------------------------------------------------------------------- diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py index caa3b00e..13137703 100755 --- a/litex/boards/targets/netv2.py +++ b/litex/boards/targets/netv2.py @@ -27,6 +27,7 @@ class _CRG(Module): self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_clk100 = ClockDomain() self.clock_domains.cd_eth = ClockDomain() # # # @@ -41,6 +42,7 @@ class _CRG(Module): pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_clk100, 100e6) pll.create_clkout(self.cd_eth, 50e6) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) -- 2.30.2