From a9dcad70ae12b556c22bde3a6e5ca13611048c2c Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 31 Jul 2019 21:51:40 +0100
Subject: [PATCH] update comments

---
 src/ieee754/fpdiv/divstages.py | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/ieee754/fpdiv/divstages.py b/src/ieee754/fpdiv/divstages.py
index 2096a667..46d9629c 100644
--- a/src/ieee754/fpdiv/divstages.py
+++ b/src/ieee754/fpdiv/divstages.py
@@ -1,5 +1,15 @@
 """IEEE754 Floating Point pipelined Divider
 
+This module simply constructs register-based pipeline(s) out of
+appropriate combinatorial blocks: setup, intermediary and final
+single-clock pipelines.
+
+"actual" processing is carried out by the DivPipeCalculateStage
+combinatorial block: everything else is chaining and pre- and post-
+data formatting.
+
+there's no "actual" work done here: it's just a "joining-together" job.
+
 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
 
 """
-- 
2.30.2