From aa34bd0bc5d7e81c50f23da036110cfe7740fea1 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 25 Feb 2022 18:20:49 +0000 Subject: [PATCH] set name of DFI interface to ecp5phy in ECP5DDRPHY --- gram/dfii.py | 2 +- gram/phy/ecp5ddrphy.py | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/gram/dfii.py b/gram/dfii.py index a1f5ad4..f9d4de5 100644 --- a/gram/dfii.py +++ b/gram/dfii.py @@ -59,7 +59,7 @@ class PhaseInjector(Elaboratable): class DFIInjector(Elaboratable): def __init__(self, csr_bank, addressbits, bankbits, nranks, databits, nphases=1): - print ("nranks", nranks, "nphases", nphases) + print ("nranks", nranks, "nphases", nphases, "addressbits", addressbits) self._nranks = nranks self._inti = dfi.Interface(addressbits, bankbits, diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py index 672d8b2..f35b760 100644 --- a/gram/phy/ecp5ddrphy.py +++ b/gram/phy/ecp5ddrphy.py @@ -143,7 +143,8 @@ class ECP5DDRPHY(Peripheral, Elaboratable): if hasattr(self.pads, "cs") and hasattr(self.pads.cs, "o0"): nranks = len(self.pads.cs.o0) databits = len(self.pads.dq.io) - self.dfi = Interface(addressbits, bankbits, nranks, 4*databits, 4) + self.dfi = Interface(addressbits, bankbits, nranks, 4*databits, 4, + name="ecp5phy") # PHY settings ----------------------------------------------------------------------------- tck = 1/(2*self._sys_clk_freq) -- 2.30.2