From aa5a53640a1e889b50a16b4ad5d59acede704417 Mon Sep 17 00:00:00 2001
From: Cesar Strauss <cestrauss@gmail.com>
Date: Fri, 1 Jan 2021 14:46:35 -0300
Subject: [PATCH] Add CR to the output data port

---
 src/soc/experiment/alu_hier.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index 83354d44..a780dd86 100644
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -208,6 +208,7 @@ class ALU(Elaboratable):
         self.p.data_i.a = self.a
         self.p.data_i.b = self.b
         self.n.data_o.o = self.o
+        self.n.data_o.cr = self.cr
 
     def elaborate(self, platform):
         m = Module()
-- 
2.30.2