From aa5d4e1eaaaf41b9e99d591dc5219289c24871a4 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 8 Jul 2022 14:24:38 +0100 Subject: [PATCH] accidental use of OpenPOWER ISA not Power ISA --- openpower/sv/overview.mdwn | 38 ++++++++++++++++++++------------------ 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn index dd9d2846f..d9d65fef7 100644 --- a/openpower/sv/overview.mdwn +++ b/openpower/sv/overview.mdwn @@ -1,16 +1,18 @@ # SV Overview -**SV is in DRAFT STATUS**. SV has not yet been submitted to the OpenPOWER Foundation ISA WG for review. +**SV is in DRAFT STATUS**. SV has not yet been submitted to the OpenPOWER +Foundation ISA WG for review. This document provides an overview and introduction as to why SV (a -[[!wikipedia Cray]]-style Vector augmentation to [[!wikipedia OpenPOWER]]) exists, and how it works. +[[!wikipedia Cray]]-style Vector augmentation to +[[!wikipedia OpenPOWER]]) exists, and how it works. **Sponsored by NLnet under the Privacy and Enhanced Trust Programme** Links: * This page: [http://libre-soc.org/openpower/sv/overview](http://libre-soc.org/openpower/sv/overview) -* [FOSDEM2021 SimpleV for OpenPOWER](https://fosdem.org/2021/schedule/event/the_libresoc_project_simple_v_vectorisation/) +* [FOSDEM2021 SimpleV for Power ISA](https://fosdem.org/2021/schedule/event/the_libresoc_project_simple_v_vectorisation/) * FOSDEM2021 presentation * [[discussion]] and [bugreport](https://bugs.libre-soc.org/show_bug.cgi?id=556) @@ -99,7 +101,7 @@ Higher performance systems may deploy SIMD backends, multi-issue and out-of-order execution, although it is strongly recommended to add predication capability directly into SIMD backend units. -In OpenPOWER ISA v3.0B pseudo-code form, an ADD operation, assuming both +In Power ISA v3.0B pseudo-code form, an ADD operation, assuming both source and destination have been "tagged" as Vectors, is simply: for i = 0 to VL-1: @@ -115,14 +117,14 @@ additional instructions have been added, almost all of them SIMD. RISC-V RVV as of version 0.9 is over 188 instructions (more than the rest of RV64G combined: 80 for RV64G and 27 for C). Over 95% of that -functionality is added to OpenPOWER v3 0B, by SimpleV augmentation, +functionality is added to Power v3.0B, by SimpleV augmentation, with around 5 to 8 instructions. -Even in OpenPOWER v3.0B, the Scalar Integer ISA is around 150 +Even in Power ISA v3.0B, the Scalar Integer ISA is around 150 instructions, with IEEE754 FP adding approximately 80 more. VSX, being based on SIMD design principles, adds somewhere in the region of 600 more. SimpleV again provides over 95% of VSX functionality, simply by augmenting -the *Scalar* OpenPOWER ISA, and in the process providing features such +the *Scalar* Power ISA, and in the process providing features such as predication, which VSX is entirely missing. AVX512, SVE2, VSX, RVV, all of these systems have to provide different @@ -130,7 +132,7 @@ types of register files: Scalar and Vector is the minimum. AVX512 even provides a mini mask regfile, followed by explicit instructions that handle operations on each of them *and map between all of them*. SV simply not only uses the existing scalar regfiles (including CRs), -but because operations exist within OpenPOWER to cover interactions +but because operations exist within Power ISA to cover interactions between the scalar regfiles (`mfcr`, `fcvt`) there is very little that needs to be added. @@ -161,7 +163,7 @@ The rest of this document builds on the above simple loop to add: * A completely new concept: "Twin Predication" * vec2/3/4 "Subvectors" and Swizzling (standard fare for 3D) -All of this is *without modifying the OpenPOWER v3.0B ISA*, except to add +All of this is *without modifying the Power v3.0B ISA*, except to add "wrapping context", similar to how v3.1B 64 Prefixes work. # Adding Scalar / Vector @@ -245,7 +247,7 @@ Condition Registers have a slightly different scheme, along the same principle, which takes into account the fact that each CR may be bit-level addressed by Condition Register operations. -Readers familiar with OpenPOWER will know of Rc=1 operations that create +Readers familiar with the Power ISA will know of Rc=1 operations that create an associated post-result "test", placing this test into an implicit Condition Register. The original researchers who created the POWER ISA chose CR0 for Integer, and CR1 for Floating Point. These *also become @@ -289,7 +291,7 @@ one single entry from a Vector. If all three registers are marked as Vector then the "traditional" predicated Vector behaviour is provided. Yet, just as before, all other options are still provided, right the way back to the pure-scalar case, -as if this were a straight OpenPOWER v3.0B non-augmented instruction. +as if this were a straight Power ISA v3.0B non-augmented instruction. Single Predication therefore provides several modes traditionally seen in Vector ISAs: @@ -348,7 +350,7 @@ example) 64 bit operations (only). The override widths are 8, 16 and 32 for integer, and FP16 and FP32 for IEEE754 (with BF16 to be added in the future). -This presents a particularly intriguing conundrum given that the OpenPOWER +This presents a particularly intriguing conundrum given that the Power Scalar ISA was never designed with for example 8 bit operations in mind, let alone Vectors of 8 bit. @@ -370,7 +372,7 @@ structure, where all types uint16_t etc. are in little-endian order: uint8_t b[0]; // array of type uint8_t uint16_t s[0]; // array of LE ordered uint16_t uint32_t i[0]; - uint64_t l[0]; // default OpenPOWER ISA uses this + uint64_t l[0]; // default Power ISA uses this } reg_t; reg_t int_regfile[128]; // SV extends to 128 regs @@ -521,7 +523,7 @@ Consequently it becomes critically important to decide a byte-order. That decision was - arbitrarily - LE mode. Actually it wasn't arbitrary at all: it was such hell to implement BE supported interpretations of CRs and LD/ST in LibreSOC, based on a terse spec that provides insufficient -clarity and assumes significant working knowledge of OpenPOWER, with +clarity and assumes significant working knowledge of the Power ISA, with arbitrary insertions of 7-index here and 3-bitindex there, the decision to pick LE was extremely easy. @@ -792,7 +794,7 @@ VGATHER/VSCATTER. # CR predicate result analysis -OpenPOWER has Condition Registers. These store an analysis of the result +Power ISA has Condition Registers. These store an analysis of the result of an operation to test it for being greater, less than or equal to zero. What if a test could be done, similar to branch BO testing, which hooked into the predication system? @@ -973,16 +975,16 @@ The other key question is of course: what's the actual instruction format, and what's in it? Bearing in mind that this requires OPF review, the current draft is at the [[sv/svp64]] page, and includes space for all the different modes, the predicates, element width overrides, SUBVL and the -register extensions, in 24 bits. This just about fits into an OpenPOWER +register extensions, in 24 bits. This just about fits into a Power v3.1B 64 bit Prefix by borrowing some of the Reserved Encoding space. -The v3.1B suffix - containing as it does a 32 bit OpenPOWER instruction - +The v3.1B suffix - containing as it does a 32 bi Power instruction - aligns perfectly with SV. Further reading is at the main [[SV|sv]] page. # Conclusion -Starting from a scalar ISA - OpenPOWER v3.0B - it was shown above that, +Starting from a scalar ISA - Power v3.0B - it was shown above that, with conceptual sub-loops, a Scalar ISA can be turned into a Vector one, by embedding Scalar instructions - unmodified - into a Vector "context" using "Prefixing". With careful thought, this technique reaches 90% -- 2.30.2