From aa931bd10b0d9e1c03aefa75abc1791d1953d716 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 9 Jul 2020 13:34:07 +0100 Subject: [PATCH] resolving issues with div tests (turned out to be nmutil.divmod) adding more tests to track down a CR0 issue --- src/soc/fu/div/test/test_pipe_caller.py | 24 +++++++++++++++++++++++ src/soc/simulator/test_div_sim.py | 26 +++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py index fb6a4025..2fe7ac08 100644 --- a/src/soc/fu/div/test/test_pipe_caller.py +++ b/src/soc/fu/div/test/test_pipe_caller.py @@ -75,6 +75,30 @@ class DIVTestCase(FHDLTestCase): tc = TestCase(prog, self.test_name, initial_regs, initial_sprs) self.test_data.append(tc) + def test_0_regression(self): + for i in range(40): + lst = ["divwo 3, 1, 2"] + initial_regs = [0] * 32 + initial_regs[1] = 0xbc716835f32ac00c + initial_regs[2] = 0xcdf69a7f7042db66 + self.run_tst_program(Program(lst), initial_regs) + + def test_0_regression(self): + for i in range(40): + lst = ["divwo 3, 1, 2"] + initial_regs = [0] * 32 + initial_regs[1] = 0x10000000000000000-4 + initial_regs[2] = 0x10000000000000000-2 + self.run_tst_program(Program(lst), initial_regs) + + def test_0_regression(self): + for i in range(40): + lst = ["divwo 3, 1, 2"] + initial_regs = [0] * 32 + initial_regs[1] = 0xffffffffffff9321 + initial_regs[2] = 0xffffffffffff7012 + self.run_tst_program(Program(lst), initial_regs) + def test_rand_divw(self): insns = ["divw", "divw.", "divwo", "divwo."] for i in range(40): diff --git a/src/soc/simulator/test_div_sim.py b/src/soc/simulator/test_div_sim.py index 610f7f86..a6f18601 100644 --- a/src/soc/simulator/test_div_sim.py +++ b/src/soc/simulator/test_div_sim.py @@ -32,6 +32,22 @@ class DivTestCases(FHDLTestCase): with Program(lst) as program: self.run_tst_program(program, [1, 2, 3]) + def test_1_divw_(self): + lst = ["addi 1, 0, 0x5678", + "addi 2, 0, 0x1234", + "divw. 3, 1, 2", + ] + with Program(lst) as program: + self.run_tst_program(program, [1, 2, 3]) + + def test_2_divw_(self): + lst = ["addi 1, 0, 0x1234", + "addi 2, 0, 0x5678", + "divw. 3, 1, 2", + ] + with Program(lst) as program: + self.run_tst_program(program, [1, 2, 3]) + def test_1_divwe(self): lst = ["addi 1, 0, 0x5678", "addi 2, 0, 0x1234", @@ -56,6 +72,16 @@ class DivTestCases(FHDLTestCase): with Program(lst) as program: self.run_tst_program(program, [1, 2, 3]) + def test_5_div_regression(self): + lst = ["addi 1, 0, 0x4", + "addi 2, 0, 0x2", + "neg 2, 2", + "neg 1, 1", + "divwo 3, 1, 2", + ] + with Program(lst) as program: + self.run_tst_program(program, [1, 2, 3]) + def run_tst_program(self, prog, initial_regs=None, initial_sprs=None, initial_mem=None): initial_regs = [0] * 32 -- 2.30.2