From aaa2146e07f1a2f7813f902432b417b0251d7233 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 2 Sep 2021 16:05:47 +0100 Subject: [PATCH] --- openpower/sv/branches.mdwn | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn index 554a90924..ac478ebd5 100644 --- a/openpower/sv/branches.mdwn +++ b/openpower/sv/branches.mdwn @@ -166,7 +166,7 @@ in significant changes as to how SVP64 is fundamentally applied, except with respect to early-out opportunities and CTR-testing, which are outlined below. -# Description and Modes +# Horizontal-First and Vertical-First Modes In SVP64 Horizontal-First Mode, the first failure in ALL mode (Great Big AND) results in early exit: no more updates to CTR occur (if requested); @@ -186,6 +186,8 @@ behaviour. Given that only one element is being tested at a time in Vertical-First Mode, a test designed to be done on multiple bits is meaningless. +# Description and Modes + Predication in both INT and CR modes may be applied to `sv.bc` and other SVP64 Branch Conditional operations, exactly as they may be applied to other SVP64 operations. When `sz` is zero, any masked-out Branch-element -- 2.30.2