From aaaf24c6f41801d9f270589b62277179f724dee5 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 13 Feb 2021 12:27:08 +0000
Subject: [PATCH] add SVP64 TestIssuer separate unit test

---
 src/soc/fu/alu/{ => test}/svp64_cases.py |  2 +-
 src/soc/simple/test/test_issuer_svp64.py | 24 ++++++++++++++++++++++++
 2 files changed, 25 insertions(+), 1 deletion(-)
 rename src/soc/fu/alu/{ => test}/svp64_cases.py (95%)
 create mode 100644 src/soc/simple/test/test_issuer_svp64.py

diff --git a/src/soc/fu/alu/svp64_cases.py b/src/soc/fu/alu/test/svp64_cases.py
similarity index 95%
rename from src/soc/fu/alu/svp64_cases.py
rename to src/soc/fu/alu/test/svp64_cases.py
index f6ed2720..bf785010 100644
--- a/src/soc/fu/alu/svp64_cases.py
+++ b/src/soc/fu/alu/test/svp64_cases.py
@@ -6,7 +6,7 @@ from soc.decoder.isa.caller import special_sprs
 from soc.sv.trans.svp64 import SVP64Asm
 
 
-class ALUTestCase(TestAccumulatorBase):
+class SVP64ALUTestCase(TestAccumulatorBase):
 
     def case_1_sv_add(self):
         # adds:
diff --git a/src/soc/simple/test/test_issuer_svp64.py b/src/soc/simple/test/test_issuer_svp64.py
new file mode 100644
index 00000000..3e64f7a9
--- /dev/null
+++ b/src/soc/simple/test/test_issuer_svp64.py
@@ -0,0 +1,24 @@
+"""test of SVP64 operations.
+
+related bugs:
+
+ * https://bugs.libre-soc.org/show_bug.cgi?id=363
+"""
+
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+
+import unittest
+from soc.simple.test.test_runner import TestRunner
+
+# test with ALU data and Logical data
+from soc.fu.alu.test.svp64_cases import SVP64ALUTestCase
+
+
+if __name__ == "__main__":
+    unittest.main(exit=False)
+    suite = unittest.TestSuite()
+    suite.addTest(TestRunner(SVP64ALUTestCase().test_data))
+
+    runner = unittest.TextTestRunner()
+    runner.run(suite)
-- 
2.30.2