From aabb36fdd58ff891e3a0946e2326d458f5a4d832 Mon Sep 17 00:00:00 2001 From: Pauli Nieminen Date: Sun, 30 Aug 2009 22:08:38 +0300 Subject: [PATCH] r600: Convert to shared debug code and add a few new debug messages. There is only a few functions that have debugging enabled now. --- src/mesa/drivers/dri/r600/Makefile | 9 +-- src/mesa/drivers/dri/r600/r600_context.c | 10 ++- src/mesa/drivers/dri/r600/r600_emit.c | 28 ++++---- src/mesa/drivers/dri/r600/r600_tex.c | 20 +++--- src/mesa/drivers/dri/r600/r600_texstate.c | 8 +-- src/mesa/drivers/dri/r600/r700_assembler.c | 72 ++++++++++----------- src/mesa/drivers/dri/r600/r700_chip.c | 34 ++++++++++ src/mesa/drivers/dri/r600/r700_clear.c | 5 +- src/mesa/drivers/dri/r600/r700_debug.c | 35 ++-------- src/mesa/drivers/dri/r600/r700_debug.h | 60 +---------------- src/mesa/drivers/dri/r600/r700_oglprog.c | 6 ++ src/mesa/drivers/dri/r600/r700_render.c | 10 ++- src/mesa/drivers/dri/r600/r700_shaderinst.c | 14 ++-- src/mesa/drivers/dri/r600/r700_vertprog.c | 3 +- 14 files changed, 141 insertions(+), 173 deletions(-) diff --git a/src/mesa/drivers/dri/r600/Makefile b/src/mesa/drivers/dri/r600/Makefile index 3c3100ab914..d925a2dfe39 100644 --- a/src/mesa/drivers/dri/r600/Makefile +++ b/src/mesa/drivers/dri/r600/Makefile @@ -27,16 +27,17 @@ COMMON_SOURCES = \ ../common/dri_util.c RADEON_COMMON_SOURCES = \ - radeon_texture.c \ + radeon_bo_legacy.c \ radeon_common_context.c \ radeon_common.c \ + radeon_cs_legacy.c \ radeon_dma.c \ + radeon_debug.c \ + radeon_fbo.c \ radeon_lock.c \ - radeon_bo_legacy.c \ - radeon_cs_legacy.c \ radeon_mipmap_tree.c \ radeon_span.c \ - radeon_fbo.c \ + radeon_texture.c \ radeon_queryobj.c DRIVER_SOURCES = \ diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 6a066f35105..251c124cbf4 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -56,6 +56,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "drivers/common/driverfuncs.h" +#include "radeon_debug.h" #include "r600_context.h" #include "radeon_common_context.h" #include "radeon_span.h" @@ -225,8 +226,10 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, /* Allocate the R600 context */ r600 = (context_t*) CALLOC(sizeof(*r600)); - if (!r600) + if (!r600) { + radeon_error("Failed to allocate memory for context.\n"); return GL_FALSE; + } if (!(screen->chip_flags & RADEON_CHIPSET_TCL)) hw_tcl_on = future_hw_tcl_on = 0; @@ -255,6 +258,7 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, if (!radeonInitContext(&r600->radeon, &functions, glVisual, driContextPriv, sharedContextPrivate)) { + radeon_error("Initializing context failed.\n"); FREE(r600); return GL_FALSE; } @@ -347,6 +351,8 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, ctx->VertexProgram._MaintainTnlProgram = GL_TRUE; ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE; + radeon_init_debug(); + driInitExtensions(ctx, card_extensions, GL_TRUE); if (r600->radeon.radeonScreen->kernel_mm) driInitExtensions(ctx, mm_extensions, GL_FALSE); @@ -375,7 +381,7 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual, TNL_CONTEXT(ctx)->Driver.RunPipeline = r600RunPipeline; if (driQueryOptionb(&r600->radeon.optionCache, "no_rast")) { - fprintf(stderr, "disabling 3D acceleration\n"); + radeon_warning("disabling 3D acceleration\n"); #if R200_MERGED FALLBACK(&r600->radeon, RADEON_FALLBACK_DISABLE, 1); #endif diff --git a/src/mesa/drivers/dri/r600/r600_emit.c b/src/mesa/drivers/dri/r600/r600_emit.c index f8c56e7774b..5c250c2418a 100644 --- a/src/mesa/drivers/dri/r600/r600_emit.c +++ b/src/mesa/drivers/dri/r600/r600_emit.c @@ -60,28 +60,30 @@ GLboolean r600EmitShader(GLcontext * ctx, radeonContextPtr radeonctx = RADEON_CONTEXT(ctx); struct radeon_bo * pbo; uint32_t *out; - shader_again_alloc: pbo = radeon_bo_open(radeonctx->radeonScreen->bom, - 0, - sizeinDWORD * 4, - 256, - RADEON_GEM_DOMAIN_GTT, - 0); + 0, + sizeinDWORD * 4, + 256, + RADEON_GEM_DOMAIN_GTT, + 0); + + radeon_print(RADEON_SHADER, RADEON_NORMAL, "%s %p size %d: %s\n", __func__, pbo, sizeinDWORD, szShaderUsage); if (!pbo) { + radeon_print(RADEON_MEMORY | RADEON_CS, RADEON_IMPORTANT, "No memory for buffer object. Flushing command buffer.\n"); rcommonFlushCmdBuf(radeonctx, __FUNCTION__); goto shader_again_alloc; } radeon_cs_space_add_persistent_bo(radeonctx->cmdbuf.cs, - pbo, - RADEON_GEM_DOMAIN_GTT, 0); + pbo, + RADEON_GEM_DOMAIN_GTT, 0); - if (radeon_cs_space_check_with_bo(radeonctx->cmdbuf.cs, - pbo, - RADEON_GEM_DOMAIN_GTT, 0)) { - fprintf(stderr,"failure to revalidate BOs - badness\n"); + if (radeon_cs_space_check_with_bo(radeonctx->cmdbuf.cs, + pbo, + RADEON_GEM_DOMAIN_GTT, 0)) { + radeon_error("failure to revalidate BOs - badness\n"); return GL_FALSE; } @@ -103,6 +105,8 @@ GLboolean r600DeleteShader(GLcontext * ctx, { struct radeon_bo * pbo = (struct radeon_bo *)shaderbo; + radeon_print(RADEON_SHADER, RADEON_NORMAL, "%s: %p\n", __func__, pbo); + if (pbo) { if (pbo->ptr) radeon_bo_unmap(pbo); diff --git a/src/mesa/drivers/dri/r600/r600_tex.c b/src/mesa/drivers/dri/r600/r600_tex.c index a06a1fa9214..d105b90cd18 100644 --- a/src/mesa/drivers/dri/r600/r600_tex.c +++ b/src/mesa/drivers/dri/r600/r600_tex.c @@ -67,7 +67,7 @@ static unsigned int translate_wrap_mode(GLenum wrapmode) case GL_MIRROR_CLAMP_TO_EDGE_EXT: return SQ_TEX_MIRROR_ONCE_LAST_TEXEL; case GL_MIRROR_CLAMP_TO_BORDER_EXT: return SQ_TEX_MIRROR_ONCE_BORDER; default: - _mesa_problem(NULL, "bad wrap mode in %s", __FUNCTION__); + radeon_error("bad wrap mode in %s", __FUNCTION__); return 0; } } @@ -208,8 +208,7 @@ static void r600SetTexFilter(radeonTexObjPtr t, GLenum minf, GLenum magf, GLfloa | R300_TX_MIN_FILTER_ANISO | R300_TX_MIN_FILTER_MIP_LINEAR | aniso_filter(anisotropy);*/ - if (RADEON_DEBUG & DEBUG_TEXTURE) - fprintf(stderr, "Using maximum anisotropy of %f\n", anisotropy); + radeon_print(RADEON_TEXTURE, RADEON_NORMAL, "Using maximum anisotropy of %f\n", anisotropy); return; } @@ -288,10 +287,9 @@ static void r600TexParameter(GLcontext * ctx, GLenum target, { radeonTexObj* t = radeon_tex_obj(texObj); - if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) { - fprintf(stderr, "%s( %s )\n", __FUNCTION__, + radeon_print(RADEON_STATE | RADEON_TEXTURE, RADEON_VERBOSE, + "%s( %s )\n", __FUNCTION__, _mesa_lookup_enum_by_nr(pname)); - } switch (pname) { case GL_TEXTURE_MIN_FILTER: @@ -351,11 +349,10 @@ static void r600DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj) context_t* rmesa = R700_CONTEXT(ctx); radeonTexObj* t = radeon_tex_obj(texObj); - if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) { - fprintf(stderr, "%s( %p (target = %s) )\n", __FUNCTION__, + radeon_print(RADEON_STATE | RADEON_TEXTURE, RADEON_NORMAL, + "%s( %p (target = %s) )\n", __FUNCTION__, (void *)texObj, _mesa_lookup_enum_by_nr(texObj->Target)); - } if (rmesa) { int i; @@ -393,10 +390,9 @@ static struct gl_texture_object *r600NewTextureObject(GLcontext * ctx, radeonTexObj* t = CALLOC_STRUCT(radeon_tex_obj); - if (RADEON_DEBUG & (DEBUG_STATE | DEBUG_TEXTURE)) { - fprintf(stderr, "%s( %p (target = %s) )\n", __FUNCTION__, + radeon_print(RADEON_STATE | RADEON_TEXTURE, RADEON_NORMAL, + "%s( %p (target = %s) )\n", __FUNCTION__, t, _mesa_lookup_enum_by_nr(target)); - } _mesa_initialize_texture_object(&t->base, name, target); t->base.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy; diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index 9f1bf45246f..237eaa8249b 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -567,7 +567,7 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex if (!t->image_override) { if (!r600GetTexFormat(texObj, firstImage->TexFormat->MesaFormat)) { - _mesa_problem(NULL, "unexpected texture format in %s", + radeon_error("unexpected texture format in %s\n", __FUNCTION__); return; } @@ -593,7 +593,7 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex SETfield(t->SQ_TEX_RESOURCE1, 0, TEX_DEPTH_shift, TEX_DEPTH_mask); break; default: - _mesa_problem(NULL, "unexpected texture target type in %s", __FUNCTION__); + radeon_error("unexpected texture target type in %s\n", __FUNCTION__); return; } @@ -675,9 +675,7 @@ GLboolean r600ValidateBuffers(GLcontext * ctx) continue; if (!r600_validate_texture(ctx, ctx->Texture.Unit[i]._Current)) { - _mesa_warning(ctx, - "failed to validate texture for unit %d.\n", - i); + radeon_warning("failed to validate texture for unit %d.\n", i); } t = radeon_tex_obj(ctx->Texture.Unit[i]._Current); if (t->image_override && t->bo) diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c index 834c23593b4..2d8480daaf7 100644 --- a/src/mesa/drivers/dri/r600/r700_assembler.c +++ b/src/mesa/drivers/dri/r600/r700_assembler.c @@ -33,8 +33,8 @@ #include "main/mtypes.h" #include "main/imports.h" +#include "radeon_debug.h" #include "r600_context.h" -#include "r700_debug.h" #include "r700_assembler.h" @@ -366,8 +366,8 @@ unsigned int r700GetNumOperands(r700_AssemblerBase* pAsm) case SQ_OP2_INST_COS: return 1; - default: r700_error(TODO_ASM_NEEDIMPINST, - "Need instruction operand number. \n");; + default: radeon_error( + "Need instruction operand number for %x.\n", pAsm->D.dst.opcode); }; return 3; @@ -531,7 +531,7 @@ int check_current_clause(r700_AssemblerBase* pAsm, case CF_EMPTY_CLAUSE: break; default: - r700_error(ERROR_ASM_VTX_CLAUSE, + radeon_error( "Unknown CF_CLAUSE_TYPE (%d) in check_current_clause. \n", (int) new_clause_type); return GL_FALSE; } @@ -565,7 +565,7 @@ int check_current_clause(r700_AssemblerBase* pAsm, } else { - r700_error(ERROR_ASM_ALLOCEXPORTCF, + radeon_error( "Error allocating new EXPORT CF instruction in check_current_clause. \n"); return GL_FALSE; } @@ -578,7 +578,7 @@ int check_current_clause(r700_AssemblerBase* pAsm, pAsm->cf_current_clause_type = CF_OTHER_CLAUSE; break; default: - r700_error(ERROR_ASM_UNKOWNCLAUSE, + radeon_error( "Unknown CF_CLAUSE_TYPE (%d) in check_current_clause. \n", (int) new_clause_type); return GL_FALSE; } @@ -611,7 +611,7 @@ GLboolean add_vfetch_instruction(r700_AssemblerBase* pAsm, } else { - r700_error(ERROR_ASM_ALLOCVTXCF, "Could not allocate a new VFetch CF instruction."); + radeon_error("Could not allocate a new VFetch CF instruction.\n"); return GL_FALSE; } @@ -661,7 +661,7 @@ GLboolean add_tex_instruction(r700_AssemblerBase* pAsm, } else { - r700_error(ERROR_ASM_ALLOCTEXCF, "Could not allocate a new TEX CF instruction."); + radeon_error("Could not allocate a new TEX CF instruction.\n"); return GL_FALSE; } @@ -1047,7 +1047,7 @@ GLboolean assemble_src(r700_AssemblerBase *pAsm, } break; default: - r700_error(ERROR_ASM_SRCARGUMENT, "Invalid source argument type"); + radeon_error("Invalid source argument type\n"); return GL_FALSE; } } @@ -1094,7 +1094,7 @@ GLboolean assemble_dst(r700_AssemblerBase *pAsm) } break; default: - r700_error(ERROR_ASM_DSTARGUMENT, "Invalid destination output argument type"); + radeon_error("Invalid destination output argument type\n"); return GL_FALSE; } @@ -1134,7 +1134,7 @@ GLboolean tex_dst(r700_AssemblerBase *pAsm) } else { - r700_error(ERROR_ASM_DSTARGUMENT, "Invalid destination output argument type"); + radeon_error("Invalid destination output argument type\n"); return GL_FALSE; } @@ -1188,7 +1188,7 @@ GLboolean tex_src(r700_AssemblerBase *pAsm) } else { - r700_error(ERROR_ASM_BADTEXSRC, "Invalid source texcoord for TEX instruction"); + radeon_error("Invalid source texcoord for TEX instruction\n"); return GL_FALSE; } @@ -1269,7 +1269,7 @@ GLboolean assemble_tex_instruction(r700_AssemblerBase *pAsm, GLboolean normalize } else { - r700_error(ERROR_ASM_TEXDSTBADTYPE, "Only temp destination registers supported for TEX dest regs."); + radeon_error("Only temp destination registers supported for TEX dest regs.\n"); return GL_FALSE; } @@ -1362,7 +1362,7 @@ GLboolean assemble_alu_src(R700ALUInstruction* alu_instruction_ptr, } else { - r700_error(ERROR_ASM_ALUSRCBADTYPE, "Source (%d) register type (%d) not one of TEMP, INPUT, or CONSTANT.", + radeon_error("Source (%d) register type (%d) not one of TEMP, INPUT, or CONSTANT.\n", source_index, pSource->rtype); return GL_FALSE; } @@ -1397,7 +1397,7 @@ GLboolean assemble_alu_src(R700ALUInstruction* alu_instruction_ptr, src_chan = SQ_CHAN_X; break; default: - r700_error(ERROR_ASM_ALUSRCSELECT, "Unknown source select value (%d) in assemble_alu_src()."); + radeon_error("Unknown source select value (%d) in assemble_alu_src().\n", channel_swizzle); return GL_FALSE; break; } @@ -1432,7 +1432,7 @@ GLboolean assemble_alu_src(R700ALUInstruction* alu_instruction_ptr, alu_instruction_ptr->m_Word1_OP3.f.src2_neg = src_neg; break; default: - r700_error(ERROR_ASM_ALUSRCNUMBER, "Only three sources allowed in ALU opcodes."); + radeon_error("Only three sources allowed in ALU opcodes.\n"); return GL_FALSE; break; } @@ -1467,7 +1467,7 @@ GLboolean add_alu_instruction(r700_AssemblerBase* pAsm, } else { - r700_error(ERROR_ASM_ALLOCALUCF, "Could not allocate a new ALU CF instruction."); + radeon_error("Could not allocate a new ALU CF instruction.\n"); return GL_FALSE; } @@ -1635,7 +1635,7 @@ GLboolean reserve_cfile(r700_AssemblerBase* pAsm, } else { - r700_error(ERROR_ASM_CONSTCHANNEL, "All cfile read ports are used, cannot reference C$sel, channel $chan."); + radeon_error("All cfile read ports are used, cannot reference C$sel, channel $chan.\n"); return GL_FALSE; } return GL_TRUE; @@ -1649,7 +1649,7 @@ GLboolean reserve_gpr(r700_AssemblerBase* pAsm, GLuint sel, GLuint chan, GLuint } else if(pAsm->hw_gpr[cycle][chan] != (int)sel) { - r700_error(ERROR_ASM_BADGPRRESERVE, "Another scalar operation has already used GPR read port for given channel"); + radeon_error("Another scalar operation has already used GPR read port for given channel\n"); return GL_FALSE; } @@ -1689,7 +1689,7 @@ GLboolean cycle_for_scalar_bank_swizzle(const int swiz, const int sel, GLuint* p } break; default: - r700_error(ERROR_ASM_BADSCALARBZ, "Bad Scalar bank swizzle value"); + radeon_error("Bad Scalar bank swizzle value\n"); break; } @@ -1737,7 +1737,7 @@ GLboolean cycle_for_vector_bank_swizzle(const int swiz, const int sel, GLuint* p } break; default: - r700_error(ERROR_ASM_BADVECTORBZ, "Bad Vec bank swizzle value"); + radeon_error("Bad Vec bank swizzle value\n"); return GL_FALSE; break; } @@ -2056,7 +2056,7 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) } else { - r700_error(ERROR_ASM_ALUDSTBADTYPE, "Only temp destination registers supported for ALU dest regs."); + radeon_error("Only temp destination registers supported for ALU dest regs.\n"); return GL_FALSE; } @@ -2207,13 +2207,13 @@ GLboolean next_ins(r700_AssemblerBase *pAsm) if (pILInst->TexSrcTarget == TEXTURE_RECT_INDEX) { if( GL_FALSE == assemble_tex_instruction(pAsm, GL_FALSE) ) { - r700_error(ERROR_ASM_TEXINSTRUCTION, "Error assembling TEX instruction"); + radeon_error("Error assembling TEX instruction\n"); return GL_FALSE; } } else { if( GL_FALSE == assemble_tex_instruction(pAsm, GL_TRUE) ) { - r700_error(ERROR_ASM_TEXINSTRUCTION, "Error assembling TEX instruction"); + radeon_error("Error assembling TEX instruction\n"); return GL_FALSE; } } @@ -2222,7 +2222,7 @@ GLboolean next_ins(r700_AssemblerBase *pAsm) { //ALU if( GL_FALSE == assemble_alu_instruction(pAsm) ) { - r700_error(ERROR_ASM_TEXINSTRUCTION, "Error assembling ALU instruction"); + radeon_error("Error assembling ALU instruction\n"); return GL_FALSE; } } @@ -2367,7 +2367,7 @@ GLboolean assemble_ADD(r700_AssemblerBase *pAsm) GLboolean assemble_BAD(char *opcode_str) { - r700_error(TODO_ASM_NEEDIMPINST, "Not yet implemented instruction (%s)", opcode_str); + radeon_error("Not yet implemented instruction (%s)\n", opcode_str); return GL_FALSE; } @@ -3381,7 +3381,7 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) if (GL_TRUE == src_const) { - r700_error(TODO_ASM_CONSTTEXADDR, "TODO: Texture coordinates from a constant register not supported."); + radeon_error("TODO: Texture coordinates from a constant register not supported.\n"); return GL_FALSE; } @@ -3391,7 +3391,7 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE; break; case OPCODE_TXB: - r700_error(TODO_ASM_TXB, "do not support TXB yet"); + radeon_error("do not support TXB yet\n"); return GL_FALSE; break; case OPCODE_TXP: @@ -3399,7 +3399,7 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm) pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE; break; default: - r700_error(ERROR_ASM_BADTEXINST, "Internal error: bad texture op (not TEX)"); + radeon_error("Internal error: bad texture op (not TEX)\n"); return GL_FALSE; break; } @@ -3581,12 +3581,12 @@ GLboolean AssembleInstr(GLuint uiNumberInsts, break; case OPCODE_ARL: - r700_error(TODO_ASM_NEEDIMPINST, "Not yet implemented instruction OPCODE_ARL "); + radeon_error("Not yet implemented instruction OPCODE_ARL \n"); //if ( GL_FALSE == assemble_BAD("ARL") ) return GL_FALSE; break; case OPCODE_ARR: - r700_error(TODO_ASM_NEEDIMPINST, "Not yet implemented instruction OPCODE_ARR "); + radeon_error("Not yet implemented instruction OPCODE_ARR \n"); //if ( GL_FALSE == assemble_BAD("ARR") ) return GL_FALSE; break; @@ -3617,7 +3617,7 @@ GLboolean AssembleInstr(GLuint uiNumberInsts, return GL_FALSE; break; case OPCODE_EXP: - r700_error(TODO_ASM_NEEDIMPINST, "Not yet implemented instruction OPCODE_EXP "); + radeon_error("Not yet implemented instruction OPCODE_EXP \n"); //if ( GL_FALSE == assemble_BAD("EXP") ) return GL_FALSE; break; // approx of EX2 @@ -3653,7 +3653,7 @@ GLboolean AssembleInstr(GLuint uiNumberInsts, return GL_FALSE; break; case OPCODE_LOG: - r700_error(TODO_ASM_NEEDIMPINST, "Not yet implemented instruction OPCODE_LOG "); + radeon_error("Not yet implemented instruction OPCODE_LOG \n"); //if ( GL_FALSE == assemble_BAD("LOG") ) return GL_FALSE; break; // approx of LG2 @@ -3752,7 +3752,7 @@ GLboolean AssembleInstr(GLuint uiNumberInsts, return GL_FALSE; break; case OPCODE_ELSE : - r700_error(TODO_ASM_NEEDIMPINST, "Not yet implemented instruction OPCODE_ELSE "); + radeon_error("Not yet implemented instruction OPCODE_ELSE \n"); //if ( GL_FALSE == assemble_BAD("ELSE") ) return GL_FALSE; break; @@ -3774,7 +3774,7 @@ GLboolean AssembleInstr(GLuint uiNumberInsts, return GL_TRUE; default: - r700_error(ERROR_ASM_UNKNOWNILINST, "internal: unknown instruction"); + radeon_error("internal: unknown instruction\n"); return GL_FALSE; } } @@ -3818,7 +3818,7 @@ GLboolean Process_Export(r700_AssemblerBase* pAsm, break; default: - r700_error(ERROR_ASM_BADEXPORTTYPE, "Unknown export type: %d", type); + radeon_error("Unknown export type: %d\n", type); return GL_FALSE; break; } diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 16f1a3df366..4fc624ed0b9 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -49,6 +49,8 @@ static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom) unsigned int i; BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); + for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) { radeonTexObj *t = r700->textures[i]; if (t) { @@ -93,6 +95,7 @@ static void r700SendTexSamplerState(GLcontext *ctx, struct radeon_state_atom *at R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); unsigned int i; BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) { radeonTexObj *t = r700->textures[i]; @@ -115,6 +118,7 @@ static void r700SendTexBorderColorState(GLcontext *ctx, struct radeon_state_atom R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); unsigned int i; BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) { radeonTexObj *t = r700->textures[i]; @@ -141,6 +145,7 @@ static void r700SetupVTXConstants(GLcontext * ctx, context_t *context = R700_CONTEXT(ctx); struct radeon_aos * paos = (struct radeon_aos *)pAos; BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); unsigned int uSQ_VTX_CONSTANT_WORD0_0; unsigned int uSQ_VTX_CONSTANT_WORD1_0; @@ -205,6 +210,7 @@ void r700SetupStreams(GLcontext *ctx) TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *vb = &tnl->vb; unsigned int i, j = 0; + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); R600_STATECHANGE(context, vtx); @@ -229,6 +235,7 @@ static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom) = (struct r700_vertex_program *)ctx->VertexProgram._Current; unsigned int i, j = 0; BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); if (context->radeon.tcl.aos_count == 0) return; @@ -264,6 +271,7 @@ static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *a R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_renderbuffer *rrb; BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); rrb = radeon_get_depthbuffer(&context->radeon); if (!rrb || !rrb->bo) { @@ -303,6 +311,7 @@ static void r700SendRenderTargetState(GLcontext *ctx, struct radeon_state_atom * struct radeon_renderbuffer *rrb; BATCH_LOCALS(&context->radeon); int id = 0; + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); rrb = radeon_get_colorbuffer(&context->radeon); if (!rrb || !rrb->bo) { @@ -352,6 +361,7 @@ static void r700SendPSState(GLcontext *ctx, struct radeon_state_atom *atom) R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_bo * pbo; BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context)); @@ -385,6 +395,7 @@ static void r700SendVSState(GLcontext *ctx, struct radeon_state_atom *atom) R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_bo * pbo; BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context)); @@ -416,6 +427,7 @@ static void r700SendFSState(GLcontext *ctx, struct radeon_state_atom *atom) R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); struct radeon_bo * pbo; BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); /* XXX fixme * R6xx chips require a FS be emitted, even if it's not used. @@ -457,6 +469,7 @@ static void r700SendViewportState(GLcontext *ctx, struct radeon_state_atom *atom R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); int id = 0; + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); if (id > R700_MAX_VIEWPORTS) return; @@ -489,6 +502,7 @@ static void r700SendSQConfig(GLcontext *ctx, struct radeon_state_atom *atom) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); BEGIN_BATCH_NO_AUTOSTATE(34); R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6); @@ -526,6 +540,7 @@ static void r700SendUCPState(GLcontext *ctx, struct radeon_state_atom *atom) R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); int i; + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); for (i = 0; i < R700_MAX_UCP; i++) { if (r700->ucp[i].enabled) { @@ -547,6 +562,7 @@ static void r700SendSPIState(GLcontext *ctx, struct radeon_state_atom *atom) R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); unsigned int ui; + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); BEGIN_BATCH_NO_AUTOSTATE(59 + R700_MAX_SHADER_EXPORTS); @@ -620,6 +636,7 @@ static void r700SendVGTState(GLcontext *ctx, struct radeon_state_atom *atom) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); BEGIN_BATCH_NO_AUTOSTATE(41); @@ -665,6 +682,7 @@ static void r700SendSXState(GLcontext *ctx, struct radeon_state_atom *atom) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); BEGIN_BATCH_NO_AUTOSTATE(9); R600_OUT_BATCH_REGVAL(SX_MISC, r700->SX_MISC.u32All); @@ -679,6 +697,7 @@ static void r700SendDBState(GLcontext *ctx, struct radeon_state_atom *atom) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); BEGIN_BATCH_NO_AUTOSTATE(23); R600_OUT_BATCH_REGVAL(DB_HTILE_DATA_BASE, r700->DB_HTILE_DATA_BASE.u32All); @@ -720,6 +739,7 @@ static void r700SendCBState(GLcontext *ctx, struct radeon_state_atom *atom) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) { BEGIN_BATCH_NO_AUTOSTATE(11); @@ -766,6 +786,7 @@ static void r700SendCBBlendState(GLcontext *ctx, struct radeon_state_atom *atom) R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); unsigned int ui; + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) { BEGIN_BATCH_NO_AUTOSTATE(3); @@ -796,6 +817,7 @@ static void r700SendCBBlendColorState(GLcontext *ctx, struct radeon_state_atom * context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); BEGIN_BATCH_NO_AUTOSTATE(6); R600_OUT_BATCH_REGSEQ(CB_BLEND_RED, 4); @@ -850,6 +872,7 @@ static void r700SendCLState(GLcontext *ctx, struct radeon_state_atom *atom) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); BEGIN_BATCH_NO_AUTOSTATE(12); R600_OUT_BATCH_REGVAL(PA_CL_CLIP_CNTL, r700->PA_CL_CLIP_CNTL.u32All); @@ -881,6 +904,7 @@ static void r700SendScissorState(GLcontext *ctx, struct radeon_state_atom *atom) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); BEGIN_BATCH_NO_AUTOSTATE(22); R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL, 2); @@ -913,6 +937,7 @@ static void r700SendSCState(GLcontext *ctx, struct radeon_state_atom *atom) context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); BEGIN_BATCH_NO_AUTOSTATE(15); R600_OUT_BATCH_REGVAL(R7xx_PA_SC_EDGERULE, r700->PA_SC_EDGERULE.u32All); @@ -969,6 +994,7 @@ static void r700SendVSConsts(GLcontext *ctx, struct radeon_state_atom *atom) R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); int i; BATCH_LOCALS(&context->radeon); + radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); if (r700->vs.num_consts == 0) return; @@ -999,6 +1025,7 @@ static int check_cb(GLcontext *ctx, struct radeon_state_atom *atom) if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) count += 11; + radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count); return count; } @@ -1019,6 +1046,7 @@ static int check_blnd(GLcontext *ctx, struct radeon_state_atom *atom) count += 3; } } + radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count); return count; } @@ -1034,6 +1062,7 @@ static int check_ucp(GLcontext *ctx, struct radeon_state_atom *atom) if (r700->ucp[i].enabled) count += 6; } + radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count); return count; } @@ -1045,6 +1074,7 @@ static int check_vtx(GLcontext *ctx, struct radeon_state_atom *atom) if (count) count += 6; + radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count); return count; } @@ -1059,6 +1089,7 @@ static int check_tx(GLcontext *ctx, struct radeon_state_atom *atom) if (t) count++; } + radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count); return count * 31; } @@ -1070,6 +1101,7 @@ static int check_ps_consts(GLcontext *ctx, struct radeon_state_atom *atom) if (count) count += 2; + radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count); return count; } @@ -1082,6 +1114,7 @@ static int check_vs_consts(GLcontext *ctx, struct radeon_state_atom *atom) if (count) count += 2; + radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count); return count; } @@ -1101,6 +1134,7 @@ do { \ void r600InitAtoms(context_t *context) { + radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context); context->radeon.hw.max_state_size = 10 + 5 + 14; /* start 3d, idle, cb/db flush */ /* Setup the atom linked list */ diff --git a/src/mesa/drivers/dri/r600/r700_clear.c b/src/mesa/drivers/dri/r600/r700_clear.c index 6d4ea90ccc6..c6546ab00c2 100644 --- a/src/mesa/drivers/dri/r600/r700_clear.c +++ b/src/mesa/drivers/dri/r600/r700_clear.c @@ -55,6 +55,8 @@ void r700Clear(GLcontext * ctx, GLbitfield mask) int i; struct gl_framebuffer *fb = ctx->DrawBuffer; + radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s %x\n", __func__, mask); + if( GL_TRUE == r700ClearFast(context, mask) ) { return; @@ -106,8 +108,7 @@ void r700Clear(GLcontext * ctx, GLbitfield mask) } if (swrast_mask) { - if (RADEON_DEBUG & DEBUG_FALLBACKS) - fprintf(stderr, "%s: swrast clear, mask: %x\n", + radeon_print(RADEON_FALLBACKS, RADEON_IMPORTANT, "%s: swrast clear, mask: %x\n", __FUNCTION__, swrast_mask); _swrast_Clear(ctx, swrast_mask); } diff --git a/src/mesa/drivers/dri/r600/r700_debug.c b/src/mesa/drivers/dri/r600/r700_debug.c index dabd0d2c259..cd1ba9eca3f 100644 --- a/src/mesa/drivers/dri/r600/r700_debug.c +++ b/src/mesa/drivers/dri/r600/r700_debug.c @@ -25,31 +25,8 @@ * CooperYuan , */ -#include -#include -#include -#include - -#include "main/glheader.h" - #include "r700_debug.h" -#include "r600_context.h" - -void NormalizeLogErrorCode(int nError) -{ - //TODO -} - -void r700_error(int nLocalError, char* fmt, ...) -{ - va_list args; - - NormalizeLogErrorCode(nLocalError); - - va_start(args, fmt); - fprintf(stderr, fmt, args); - va_end(args); -} +#include "radeon_debug.h" void DumpHwBinary(int type, void *addr, int size) { @@ -61,21 +38,21 @@ void DumpHwBinary(int type, void *addr, int size) switch (type) { case DUMP_PIXEL_SHADER: - DEBUGF("Pixel Shader\n"); + radeon_print(RADEON_SHADER, RADEON_TRACE, "Pixel Shader\n"); break; case DUMP_VERTEX_SHADER: - DEBUGF("Vertex Shader\n"); + radeon_print(RADEON_SHADER, RADEON_TRACE, "Vertex Shader\n"); break; case DUMP_FETCH_SHADER: - DEBUGF("Fetch Shader\n"); + radeon_print(RADEON_SHADER, RADEON_TRACE, "Fetch Shader\n"); break; } for (i = 0; i < size; i++) { - DEBUGP("0x%08x,\t", *pHw); + radeon_print(RADEON_SHADER, RADEON_TRACE, "0x%08x,\t", *pHw); if (i%4 == 3) - DEBUGP("0x%08x\n", *pHw); + radeon_print(RADEON_SHADER, RADEON_TRACE, "0x%08x\n", *pHw); pHw++; } diff --git a/src/mesa/drivers/dri/r600/r700_debug.h b/src/mesa/drivers/dri/r600/r700_debug.h index e810e6da083..c0921bf6100 100644 --- a/src/mesa/drivers/dri/r600/r700_debug.h +++ b/src/mesa/drivers/dri/r600/r700_debug.h @@ -27,67 +27,13 @@ #ifndef _R700_DEBUG_H_ #define _R700_DEBUG_H_ - -enum R700_ERROR -{ - ERROR_ASM_VTX_CLAUSE = 0x1000, - ERROR_ASM_UNKOWNCLAUSE = 0x1001, - ERROR_ASM_ALLOCEXPORTCF = 0x1002, - ERROR_ASM_ALLOCVTXCF = 0x1003, - ERROR_ASM_ALLOCTEXCF = 0x1004, - ERROR_ASM_ALLOCALUCF = 0x1005, - ERROR_ASM_UNKNOWNILINST = 0x1006, - ERROR_ASM_SRCARGUMENT = 0x1007, - ERROR_ASM_DSTARGUMENT = 0x1008, - ERROR_ASM_TEXINSTRUCTION = 0x1009, - ERROR_ASM_ALUINSTRUCTION = 0x100A, - ERROR_ASM_INSTDSTTRACK = 0x100B, - ERROR_ASM_TEXDSTBADTYPE = 0x100C, - ERROR_ASM_ALUSRCBADTYPE = 0x100D, - ERROR_ASM_ALUSRCSELECT = 0x100E, - ERROR_ASM_ALUSRCNUMBER = 0x100F, - ERROR_ASM_ALUDSTBADTYPE = 0x1010, - ERROR_ASM_CONSTCHANNEL = 0x1011, - ERROR_ASM_BADSCALARBZ = 0x1012, - ERROR_ASM_BADGPRRESERVE = 0x1013, - ERROR_ASM_BADVECTORBZ = 0x1014, - ERROR_ASM_BADTEXINST = 0x1015, - ERROR_ASM_BADTEXSRC = 0x1016, - ERROR_ASM_BADEXPORTTYPE = 0x1017, - - - TODO_ASM_CONSTTEXADDR = 0x8000, - TODO_ASM_NEEDIMPINST = 0x8001, - TODO_ASM_TXB = 0x8002, - TODO_ASM_TXP = 0x8003 -}; - enum R700_DUMP_TYPE { - DUMP_VERTEX_SHADER = 0x1, - DUMP_PIXEL_SHADER = 0x2, - DUMP_FETCH_SHADER = 0x4, + DUMP_VERTEX_SHADER = 0x1, + DUMP_PIXEL_SHADER = 0x2, + DUMP_FETCH_SHADER = 0x4, }; -#define DEBUGF printf -#define DEBUGP printf - -void NormalizeLogErrorCode(int nError); -/*NormalizeLogErrorCode(nLocalError); */ -void r700_error(int nLocalError, char *fmt, ...); extern void DumpHwBinary(int, void *, int); -#ifdef STANDALONE_COMPILER -#ifdef __cplusplus -extern "C" -{ -#endif //__cplusplus - -void LogString(char* szStr); - -#ifdef __cplusplus -} -#endif //__cplusplus -#endif /*STANDALONE_COMPILER*/ - #endif /*_R700_DEBUG_H_*/ diff --git a/src/mesa/drivers/dri/r600/r700_oglprog.c b/src/mesa/drivers/dri/r600/r700_oglprog.c index c49b90c1cc9..3c8c1fd7a34 100644 --- a/src/mesa/drivers/dri/r600/r700_oglprog.c +++ b/src/mesa/drivers/dri/r600/r700_oglprog.c @@ -49,6 +49,9 @@ static struct gl_program *r700NewProgram(GLcontext * ctx, struct r700_vertex_program *vp; struct r700_fragment_program *fp; + radeon_print(RADEON_SHADER, RADEON_VERBOSE, + "%s %u, %u\n", __func__, target, id); + switch (target) { case GL_VERTEX_STATE_PROGRAM_NV: @@ -89,6 +92,9 @@ static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog) struct r700_vertex_program * vp; struct r700_fragment_program * fp; + radeon_print(RADEON_SHADER, RADEON_VERBOSE, + "%s %p\n", __func__, prog); + switch (prog->Target) { case GL_VERTEX_STATE_PROGRAM_NV: diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 0b3ceb01bac..4753c757a13 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -327,8 +327,8 @@ static GLuint r700PredictRenderSize(GLcontext* ctx) else dwords += state_size; - if (RADEON_DEBUG & DEBUG_PRIMS) - fprintf(stderr, "%s: total prediction size is %d.\n", __FUNCTION__, dwords); + radeon_print(RADEON_RENDER, RADEON_VERBOSE, + "%s: total prediction size is %d.\n", __FUNCTION__, dwords); return dwords; } @@ -342,8 +342,7 @@ static GLboolean r700RunRender(GLcontext * ctx, struct vertex_buffer *vb = &tnl->vb; struct radeon_renderbuffer *rrb; - if (RADEON_DEBUG & DEBUG_PRIMS) - fprintf(stderr, "%s: cs begin at %d\n", + radeon_print(RADEON_RENDER, RADEON_NORMAL, "%s: cs begin at %d\n", __func__, context->radeon.cmdbuf.cs->cdw); /* always emit CB base to prevent @@ -388,8 +387,7 @@ static GLboolean r700RunRender(GLcontext * ctx, radeonReleaseArrays(ctx, ~0); - if (RADEON_DEBUG & DEBUG_PRIMS) - fprintf(stderr, "%s: cs end at %d\n", + radeon_print(RADEON_RENDER, RADEON_TRACE, "%s: cs end at %d\n", __func__, context->radeon.cmdbuf.cs->cdw); if ( emit_end < context->radeon.cmdbuf.cs->cdw ) diff --git a/src/mesa/drivers/dri/r600/r700_shaderinst.c b/src/mesa/drivers/dri/r600/r700_shaderinst.c index c1bffee91f0..f120d9f941f 100644 --- a/src/mesa/drivers/dri/r600/r700_shaderinst.c +++ b/src/mesa/drivers/dri/r600/r700_shaderinst.c @@ -27,7 +27,7 @@ #include "main/mtypes.h" -#include "r700_debug.h" +#include "radeon_debug.h" #include "r700_shaderinst.h" void Init_R700ControlFlowGenericClause(R700ControlFlowGenericClause* pInst) @@ -208,16 +208,16 @@ unsigned int GetCFMaxInstructions(ShaderInstType instType) GLboolean LinkVertexInstruction(R700ControlFlowGenericClause *pCFGeneric, R700VertexInstruction *pVTXInstruction) { - if (pCFGeneric->m_pLinkedTEXInstruction != 0) - { - r700_error(ERROR_ASM_VTX_CLAUSE, "This instruction is already linked to a texture instruction"); - return GL_FALSE; + if (pCFGeneric->m_pLinkedTEXInstruction != 0) + { + radeon_error("This instruction is already linked to a texture instruction.\n"); + return GL_FALSE; } pCFGeneric->m_pLinkedVTXInstruction = pVTXInstruction; - pVTXInstruction->m_pLinkedGenericClause = pCFGeneric; + pVTXInstruction->m_pLinkedGenericClause = pCFGeneric; - return GL_TRUE; + return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index 86a67ab766f..d107f99e7ba 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -38,6 +38,7 @@ #include "shader/prog_parameter.h" #include "shader/prog_statevars.h" +#include "radeon_debug.h" #include "r600_context.h" #include "r600_cmdbuf.h" @@ -174,7 +175,7 @@ void Map_Vertex_Program(struct r700_vertex_program *vp, // Create VFETCH instructions for inputs if (GL_TRUE != Process_Vertex_Program_Vfetch_Instructions(vp, mesa_vp) ) { - r700_error(ERROR_ASM_VTX_CLAUSE, "Calling Process_Vertex_Program_Vfetch_Instructions return error. \n"); + radeon_error("Calling Process_Vertex_Program_Vfetch_Instructions return error. \n"); return; //error } -- 2.30.2