From aade6cadcc425feddbdd200de00f1f27e2717d72 Mon Sep 17 00:00:00 2001 From: Daniel Benusovich Date: Sun, 21 Apr 2019 18:19:34 -0700 Subject: [PATCH] Add output signal to PLRU --- TLB/src/ariane/plru.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/TLB/src/ariane/plru.py b/TLB/src/ariane/plru.py index 50951c1f..ff52aace 100644 --- a/TLB/src/ariane/plru.py +++ b/TLB/src/ariane/plru.py @@ -24,6 +24,7 @@ class PLRU: # Tree (bit per entry) self.TLBSZ = 2*(self.entries-1) self.plru_tree = Signal(self.TLBSZ) + self.plru_tree_o = Signal(self.TLBSZ) def elaborate(self, platform): m = Module() @@ -58,7 +59,7 @@ class PLRU: plru_idx = idx_base + (i >> shift) print ("plru", i, lvl, hex(idx_base), plru_idx, shift, new_idx) - m.d.sync += self.plru_tree[plru_idx].eq(new_idx) + m.d.sync += self.plru_tree_o[plru_idx].eq(new_idx) # Decode tree to write enable signals # Next for-loop basically creates the following logic for e.g. -- 2.30.2