From aae9718e4d4e8d01dcee22684e82b000203d3e52 Mon Sep 17 00:00:00 2001 From: Peter Bergner Date: Thu, 4 Apr 2019 09:00:29 -0500 Subject: [PATCH] Add extended mnemonics for bctar. Fix setting of 'at' branch hints. opcodes/ PR gas/24349 * ppc-opc.c (valid_bo_pre_v2): Add comments. (valid_bo_post_v2): Add support for 'at' branch hints. (insert_bo): Only error on branch on ctr. (get_bo_hint_mask): New function. (insert_boe): Add new 'branch_taken' formal argument. Add support for inserting 'at' branch hints. (extract_boe): Add new 'branch_taken' formal argument. Add support for extracting 'at' branch hints. (insert_bom, extract_bom, insert_bop, extract_bop): New functions. (BOE): Delete operand. (BOM, BOP): New operands. (RM): Update value. (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete. (powerpc_opcodes) : Replace BOE with BOM. (powerpc_opcodes) : Replace BOE with BOP. : New extended mnemonics. gas/ PR gas/24349 * testsuite/gas/ppc/power8.s: (bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-, bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar, bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar, bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-, bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-, bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+, bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+, bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl, beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-, bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-, buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+, bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar, bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar, bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+, bttarl+): Add tests of extended mnemonics. * testsuite/gas/ppc/power8.d: Likewise. Update previous bctar tests to expect new extended mnemonics. * testsuite/gas/ppc/a2.s: : Update test to not use illegal BO value. Use a more convenient BI value. * testsuite/gas/ppc/a2.d: Update tests for new expect output. --- gas/ChangeLog | 25 +++ gas/testsuite/gas/ppc/a2.d | 29 +-- gas/testsuite/gas/ppc/a2.s | 12 +- gas/testsuite/gas/ppc/power8.d | 126 ++++++++++++- gas/testsuite/gas/ppc/power8.s | 118 +++++++++++++ opcodes/ChangeLog | 36 ++++ opcodes/ppc-opc.c | 311 +++++++++++++++++++++++++++------ 7 files changed, 584 insertions(+), 73 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index b91da2a2154..3778ef9ce03 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,28 @@ +2019-04-04 Peter Bergner + + PR gas/24349 + * testsuite/gas/ppc/power8.s: (bdnztar, bdnztarl, bdztar, bdztarl, + btar, btarl, bdnztar-, bdnztarl-, bdnztar+, bdnztarl+, bdztar-, + bdztarl-, bdztar+, bdztarl+, bgetar, bnltar, bgetarl, bnltarl, + bletar, bngtar, bletarl, bngtarl, bnetar, bnetarl, bnstar, bnutar, + bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-, bnltarl-, bletar-, + bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-, bnstar-, bnutar-, + bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+, bnltarl+, bletar+, + bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+, bnstar+, bnutar+, + bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl, beqtar, + beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-, + bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-, + buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+, + bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar, + bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar, + bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+, + bttarl+): Add tests of extended mnemonics. + * testsuite/gas/ppc/power8.d: Likewise. Update previous bctar tests + to expect new extended mnemonics. + * testsuite/gas/ppc/a2.s: : Update test + to not use illegal BO value. Use a more convenient BI value. + * testsuite/gas/ppc/a2.d: Update tests for new expect output. + 2019-04-03 Max Filippov * config/tc-xtensa.c (convert_frag_immed): Drop diff --git a/gas/testsuite/gas/ppc/a2.d b/gas/testsuite/gas/ppc/a2.d index 3e3ea2c37a6..5899edbbd85 100644 --- a/gas/testsuite/gas/ppc/a2.d +++ b/gas/testsuite/gas/ppc/a2.d @@ -46,11 +46,11 @@ Disassembly of section \.text: 88: (00 00 02 00|00 02 00 00) attn 8c: (48 00 00 02|02 00 00 48) ba 0 8c: R_PPC(|64)_ADDR24 label_abs - 90: (40 01 00 00|00 00 01 40) bdnzf gt,90 + 90: (40 8a 00 00|00 00 8a 40) bne cr2,90 90: R_PPC(|64)_REL14 foo - 94: (40 01 00 00|00 00 01 40) bdnzf gt,94 + 94: (40 ca 00 00|00 00 ca 40) bne- cr2,94 94: R_PPC(|64)_REL14 foo - 98: (40 01 00 00|00 00 01 40) bdnzf gt,98 + 98: (40 ea 00 00|00 00 ea 40) bne\+ cr2,98 98: R_PPC(|64)_REL14 foo 9c: (40 85 00 02|02 00 85 40) blea cr1,0 9c: R_PPC(|64)_ADDR14 foo_abs @@ -59,16 +59,16 @@ Disassembly of section \.text: a4: (40 e5 00 02|02 00 e5 40) blea\+ cr1,0 a4: R_PPC(|64)_ADDR14 foo_abs a8: (4c 86 0c 20|20 0c 86 4c) bcctr 4,4\*cr1\+eq,1 - ac: (4c 86 04 20|20 04 86 4c) bnectr cr1 - b0: (4c a6 04 20|20 04 a6 4c) bcctr\+ 4,4\*cr1\+eq + ac: (4c c6 04 20|20 04 c6 4c) bnectr- cr1 + b0: (4c e6 04 20|20 04 e6 4c) bnectr\+ cr1 b4: (4c 86 0c 21|21 0c 86 4c) bcctrl 4,4\*cr1\+eq,1 - b8: (4c 86 04 21|21 04 86 4c) bnectrl cr1 - bc: (4c a6 04 21|21 04 a6 4c) bcctrl\+ 4,4\*cr1\+eq - c0: (40 01 00 01|01 00 01 40) bdnzfl gt,c0 + b8: (4c c6 04 21|21 04 c6 4c) bnectrl- cr1 + bc: (4c e6 04 21|21 04 e6 4c) bnectrl\+ cr1 + c0: (40 8a 00 01|01 00 8a 40) bnel cr2,c0 c0: R_PPC(|64)_REL14 foo - c4: (40 01 00 01|01 00 01 40) bdnzfl gt,c4 + c4: (40 ca 00 01|01 00 ca 40) bnel- cr2,c4 c4: R_PPC(|64)_REL14 foo - c8: (40 01 00 01|01 00 01 40) bdnzfl gt,c8 + c8: (40 ea 00 01|01 00 ea 40) bnel\+ cr2,c8 c8: R_PPC(|64)_REL14 foo cc: (40 85 00 03|03 00 85 40) blela cr1,0 cc: R_PPC(|64)_ADDR14 foo_abs @@ -77,11 +77,11 @@ Disassembly of section \.text: d4: (40 e5 00 03|03 00 e5 40) blela\+ cr1,0 d4: R_PPC(|64)_ADDR14 foo_abs d8: (4c 86 08 20|20 08 86 4c) bclr 4,4\*cr1\+eq,1 - dc: (4c 86 00 20|20 00 86 4c) bnelr cr1 - e0: (4c a6 00 20|20 00 a6 4c) bclr\+ 4,4\*cr1\+eq + dc: (4c c6 00 20|20 00 c6 4c) bnelr- cr1 + e0: (4c e6 00 20|20 00 e6 4c) bnelr\+ cr1 e4: (4c 86 08 21|21 08 86 4c) bclrl 4,4\*cr1\+eq,1 - e8: (4c 86 00 21|21 00 86 4c) bnelrl cr1 - ec: (4c a6 00 21|21 00 a6 4c) bclrl\+ 4,4\*cr1\+eq + e8: (4c c6 00 21|21 00 c6 4c) bnelrl- cr1 + ec: (4c e6 00 21|21 00 e6 4c) bnelrl\+ cr1 f0: (48 00 00 00|00 00 00 48) b f0 f0: R_PPC(|64)_REL24 label f4: (48 00 00 03|03 00 00 48) bla 0 @@ -582,3 +582,4 @@ Disassembly of section \.text: 8a8: (7d 6a 62 78|78 62 6a 7d) xor r10,r11,r12 8ac: (69 6a 10 00|00 10 6a 69) xori r10,r11,4096 8b0: (6d 6a 10 00|00 10 6a 6d) xoris r10,r11,4096 +#pass diff --git a/gas/testsuite/gas/ppc/a2.s b/gas/testsuite/gas/ppc/a2.s index ecb8668a51a..6893ae8cfef 100644 --- a/gas/testsuite/gas/ppc/a2.s +++ b/gas/testsuite/gas/ppc/a2.s @@ -36,9 +36,9 @@ start: andis. 4,5,6 attn ba label_abs - bc 0,1,foo - bc- 0,1,foo - bc+ 0,1,foo + bc 4,10,foo + bc- 4,10,foo + bc+ 4,10,foo bca 4,5,foo_abs bca- 4,5,foo_abs bca+ 4,5,foo_abs @@ -48,9 +48,9 @@ start: bcctrl 4,6,1 bcctrl- 4,6 bcctrl+ 4,6 - bcl 0,1,foo - bcl- 0,1,foo - bcl+ 0,1,foo + bcl 4,10,foo + bcl- 4,10,foo + bcl+ 4,10,foo bcla 4,5,foo_abs bcla- 4,5,foo_abs bcla+ 4,5,foo_abs diff --git a/gas/testsuite/gas/ppc/power8.d b/gas/testsuite/gas/ppc/power8.d index 5c97ab93740..77d36813f31 100644 --- a/gas/testsuite/gas/ppc/power8.d +++ b/gas/testsuite/gas/ppc/power8.d @@ -30,10 +30,10 @@ Disassembly of section \.text: 50: (4c 00 01 24|24 01 00 4c) rfebb 0 54: (4c 00 09 24|24 09 00 4c) rfebb 58: (4c 00 09 24|24 09 00 4c) rfebb - 5c: (4d 95 04 60|60 04 95 4d) bctar- 12,4\*cr5\+gt - 60: (4c 87 04 61|61 04 87 4c) bctarl- 4,4\*cr1\+so - 64: (4d ac 04 60|60 04 ac 4d) bctar\+ 12,4\*cr3\+lt - 68: (4c a2 04 61|61 04 a2 4c) bctarl\+ 4,eq + 5c: (4d d5 04 60|60 04 d5 4d) bgttar- cr5 + 60: (4c c7 04 61|61 04 c7 4c) bnstarl- cr1 + 64: (4d ec 04 60|60 04 ec 4d) blttar\+ cr3 + 68: (4c e2 04 61|61 04 e2 4c) bnetarl\+ 6c: (4c 88 0c 60|60 0c 88 4c) bctar 4,4\*cr2\+lt,1 70: (4c 87 14 61|61 14 87 4c) bctarl 4,4\*cr1\+so,2 74: (7c 00 00 3c|3c 00 00 7c) waitasec @@ -192,4 +192,122 @@ Disassembly of section \.text: .*: (7d 81 49 2d|2d 49 81 7d) stwcx\. r12,r1,r9 .*: (7d a0 51 ad|ad 51 a0 7d) stdcx\. r13,0,r10 .*: (7d a1 51 ad|ad 51 a1 7d) stdcx\. r13,r1,r10 +.*: (4e 80 04 60|60 04 80 4e) btar +.*: (4e 80 04 60|60 04 80 4e) btar +.*: (4e 00 04 60|60 04 00 4e) bdnztar +.*: (4e 00 04 61|61 04 00 4e) bdnztarl +.*: (4e 40 04 60|60 04 40 4e) bdztar +.*: (4e 40 04 61|61 04 40 4e) bdztarl +.*: (4e 80 04 60|60 04 80 4e) btar +.*: (4e 80 04 61|61 04 80 4e) btarl +.*: (4f 00 04 60|60 04 00 4f) bdnztar- +.*: (4f 00 04 61|61 04 00 4f) bdnztarl- +.*: (4f 20 04 60|60 04 20 4f) bdnztar\+ +.*: (4f 20 04 61|61 04 20 4f) bdnztarl\+ +.*: (4f 40 04 60|60 04 40 4f) bdztar- +.*: (4f 40 04 61|61 04 40 4f) bdztarl- +.*: (4f 60 04 60|60 04 60 4f) bdztar\+ +.*: (4f 60 04 61|61 04 60 4f) bdztarl\+ +.*: (4c 90 04 60|60 04 90 4c) bgetar cr4 +.*: (4c 90 04 60|60 04 90 4c) bgetar cr4 +.*: (4c 90 04 61|61 04 90 4c) bgetarl cr4 +.*: (4c 90 04 61|61 04 90 4c) bgetarl cr4 +.*: (4c 91 04 60|60 04 91 4c) bletar cr4 +.*: (4c 91 04 60|60 04 91 4c) bletar cr4 +.*: (4c 91 04 61|61 04 91 4c) bletarl cr4 +.*: (4c 91 04 61|61 04 91 4c) bletarl cr4 +.*: (4c 92 04 60|60 04 92 4c) bnetar cr4 +.*: (4c 92 04 61|61 04 92 4c) bnetarl cr4 +.*: (4c 93 04 60|60 04 93 4c) bnstar cr4 +.*: (4c 93 04 60|60 04 93 4c) bnstar cr4 +.*: (4c 93 04 61|61 04 93 4c) bnstarl cr4 +.*: (4c 93 04 61|61 04 93 4c) bnstarl cr4 +.*: (4c d0 04 60|60 04 d0 4c) bgetar- cr4 +.*: (4c d0 04 60|60 04 d0 4c) bgetar- cr4 +.*: (4c d0 04 61|61 04 d0 4c) bgetarl- cr4 +.*: (4c d0 04 61|61 04 d0 4c) bgetarl- cr4 +.*: (4c d1 04 60|60 04 d1 4c) bletar- cr4 +.*: (4c d1 04 60|60 04 d1 4c) bletar- cr4 +.*: (4c d1 04 61|61 04 d1 4c) bletarl- cr4 +.*: (4c d1 04 61|61 04 d1 4c) bletarl- cr4 +.*: (4c d2 04 60|60 04 d2 4c) bnetar- cr4 +.*: (4c d2 04 61|61 04 d2 4c) bnetarl- cr4 +.*: (4c d3 04 60|60 04 d3 4c) bnstar- cr4 +.*: (4c d3 04 60|60 04 d3 4c) bnstar- cr4 +.*: (4c d3 04 61|61 04 d3 4c) bnstarl- cr4 +.*: (4c d3 04 61|61 04 d3 4c) bnstarl- cr4 +.*: (4c f0 04 60|60 04 f0 4c) bgetar\+ cr4 +.*: (4c f0 04 60|60 04 f0 4c) bgetar\+ cr4 +.*: (4c f0 04 61|61 04 f0 4c) bgetarl\+ cr4 +.*: (4c f0 04 61|61 04 f0 4c) bgetarl\+ cr4 +.*: (4c f1 04 60|60 04 f1 4c) bletar\+ cr4 +.*: (4c f1 04 60|60 04 f1 4c) bletar\+ cr4 +.*: (4c f1 04 61|61 04 f1 4c) bletarl\+ cr4 +.*: (4c f1 04 61|61 04 f1 4c) bletarl\+ cr4 +.*: (4c f2 04 60|60 04 f2 4c) bnetar\+ cr4 +.*: (4c f2 04 61|61 04 f2 4c) bnetarl\+ cr4 +.*: (4c f3 04 60|60 04 f3 4c) bnstar\+ cr4 +.*: (4c f3 04 60|60 04 f3 4c) bnstar\+ cr4 +.*: (4c f3 04 61|61 04 f3 4c) bnstarl\+ cr4 +.*: (4c f3 04 61|61 04 f3 4c) bnstarl\+ cr4 +.*: (4d 90 04 60|60 04 90 4d) blttar cr4 +.*: (4d 90 04 61|61 04 90 4d) blttarl cr4 +.*: (4d 91 04 60|60 04 91 4d) bgttar cr4 +.*: (4d 91 04 61|61 04 91 4d) bgttarl cr4 +.*: (4d 92 04 60|60 04 92 4d) beqtar cr4 +.*: (4d 92 04 61|61 04 92 4d) beqtarl cr4 +.*: (4d 93 04 60|60 04 93 4d) bsotar cr4 +.*: (4d 93 04 60|60 04 93 4d) bsotar cr4 +.*: (4d 93 04 61|61 04 93 4d) bsotarl cr4 +.*: (4d 93 04 61|61 04 93 4d) bsotarl cr4 +.*: (4d d0 04 60|60 04 d0 4d) blttar- cr4 +.*: (4d d0 04 61|61 04 d0 4d) blttarl- cr4 +.*: (4d d1 04 60|60 04 d1 4d) bgttar- cr4 +.*: (4d d1 04 61|61 04 d1 4d) bgttarl- cr4 +.*: (4d d2 04 60|60 04 d2 4d) beqtar- cr4 +.*: (4d d2 04 61|61 04 d2 4d) beqtarl- cr4 +.*: (4d d3 04 60|60 04 d3 4d) bsotar- cr4 +.*: (4d d3 04 60|60 04 d3 4d) bsotar- cr4 +.*: (4d d3 04 61|61 04 d3 4d) bsotarl- cr4 +.*: (4d d3 04 61|61 04 d3 4d) bsotarl- cr4 +.*: (4d f0 04 60|60 04 f0 4d) blttar\+ cr4 +.*: (4d f0 04 61|61 04 f0 4d) blttarl\+ cr4 +.*: (4d f1 04 60|60 04 f1 4d) bgttar\+ cr4 +.*: (4d f1 04 61|61 04 f1 4d) bgttarl\+ cr4 +.*: (4d f2 04 60|60 04 f2 4d) beqtar\+ cr4 +.*: (4d f2 04 61|61 04 f2 4d) beqtarl\+ cr4 +.*: (4d f3 04 60|60 04 f3 4d) bsotar\+ cr4 +.*: (4d f3 04 60|60 04 f3 4d) bsotar\+ cr4 +.*: (4d f3 04 61|61 04 f3 4d) bsotarl\+ cr4 +.*: (4d f3 04 61|61 04 f3 4d) bsotarl\+ cr4 +.*: (4c 08 04 60|60 04 08 4c) bdnzftar 4\*cr2\+lt +.*: (4c 08 04 61|61 04 08 4c) bdnzftarl 4\*cr2\+lt +.*: (4c 48 04 60|60 04 48 4c) bdzftar 4\*cr2\+lt +.*: (4c 48 04 61|61 04 48 4c) bdzftarl 4\*cr2\+lt +.*: (4c 88 04 60|60 04 88 4c) bgetar cr2 +.*: (4c 88 04 61|61 04 88 4c) bgetarl cr2 +.*: (4c c8 04 60|60 04 c8 4c) bgetar- cr2 +.*: (4c c8 04 61|61 04 c8 4c) bgetarl- cr2 +.*: (4c e8 04 60|60 04 e8 4c) bgetar\+ cr2 +.*: (4c e8 04 61|61 04 e8 4c) bgetarl\+ cr2 +.*: (4d 08 04 60|60 04 08 4d) bdnzttar 4\*cr2\+lt +.*: (4d 08 04 61|61 04 08 4d) bdnzttarl 4\*cr2\+lt +.*: (4d 48 04 60|60 04 48 4d) bdzttar 4\*cr2\+lt +.*: (4d 48 04 61|61 04 48 4d) bdzttarl 4\*cr2\+lt +.*: (4d 88 04 60|60 04 88 4d) blttar cr2 +.*: (4d 88 04 61|61 04 88 4d) blttarl cr2 +.*: (4d c8 04 60|60 04 c8 4d) blttar- cr2 +.*: (4d c8 04 61|61 04 c8 4d) blttarl- cr2 +.*: (4d e8 04 60|60 04 e8 4d) blttar\+ cr2 +.*: (4d e8 04 61|61 04 e8 4d) blttarl\+ cr2 +.*: (4d ca 04 60|60 04 ca 4d) beqtar- cr2 +.*: (4d ca 04 61|61 04 ca 4d) beqtarl- cr2 +.*: (4d ea 04 60|60 04 ea 4d) beqtar\+ cr2 +.*: (4d ea 04 61|61 04 ea 4d) beqtarl\+ cr2 +.*: (4d 89 04 60|60 04 89 4d) bgttar cr2 +.*: (4d 89 04 60|60 04 89 4d) bgttar cr2 +.*: (4d 89 1c 60|60 1c 89 4d) bctar 12,4\*cr2\+gt,3 +.*: (4d 89 04 61|61 04 89 4d) bgttarl cr2 +.*: (4d 89 04 61|61 04 89 4d) bgttarl cr2 +.*: (4d 89 1c 61|61 1c 89 4d) bctarl 12,4\*cr2\+gt,3 #pass diff --git a/gas/testsuite/gas/ppc/power8.s b/gas/testsuite/gas/ppc/power8.s index 857bda2a910..beb1c5e81c5 100644 --- a/gas/testsuite/gas/ppc/power8.s +++ b/gas/testsuite/gas/ppc/power8.s @@ -184,3 +184,121 @@ power8: stwcx. 12,1,9 stdcx. 13,0,10 stdcx. 13,1,10 + bctar 0b10100,lt + btar + bdnztar + bdnztarl + bdztar + bdztarl + btar + btarl + bdnztar- + bdnztarl- + bdnztar+ + bdnztarl+ + bdztar- + bdztarl- + bdztar+ + bdztarl+ + bgetar cr4 + bnltar cr4 + bgetarl cr4 + bnltarl cr4 + bletar cr4 + bngtar cr4 + bletarl cr4 + bngtarl cr4 + bnetar cr4 + bnetarl cr4 + bnstar cr4 + bnutar cr4 + bnstarl cr4 + bnutarl cr4 + bgetar- cr4 + bnltar- cr4 + bgetarl- cr4 + bnltarl- cr4 + bletar- cr4 + bngtar- cr4 + bletarl- cr4 + bngtarl- cr4 + bnetar- cr4 + bnetarl- cr4 + bnstar- cr4 + bnutar- cr4 + bnstarl- cr4 + bnutarl- cr4 + bgetar+ cr4 + bnltar+ cr4 + bgetarl+ cr4 + bnltarl+ cr4 + bletar+ cr4 + bngtar+ cr4 + bletarl+ cr4 + bngtarl+ cr4 + bnetar+ cr4 + bnetarl+ cr4 + bnstar+ cr4 + bnutar+ cr4 + bnstarl+ cr4 + bnutarl+ cr4 + blttar cr4 + blttarl cr4 + bgttar cr4 + bgttarl cr4 + beqtar cr4 + beqtarl cr4 + bsotar cr4 + buntar cr4 + bsotarl cr4 + buntarl cr4 + blttar- cr4 + blttarl- cr4 + bgttar- cr4 + bgttarl- cr4 + beqtar- cr4 + beqtarl- cr4 + bsotar- cr4 + buntar- cr4 + bsotarl- cr4 + buntarl- cr4 + blttar+ cr4 + blttarl+ cr4 + bgttar+ cr4 + bgttarl+ cr4 + beqtar+ cr4 + beqtarl+ cr4 + bsotar+ cr4 + buntar+ cr4 + bsotarl+ cr4 + buntarl+ cr4 + bdnzftar 4*cr2+lt + bdnzftarl 4*cr2+lt + bdzftar 4*cr2+lt + bdzftarl 4*cr2+lt + bftar 4*cr2+lt + bftarl 4*cr2+lt + bftar- 4*cr2+lt + bftarl- 4*cr2+lt + bftar+ 4*cr2+lt + bftarl+ 4*cr2+lt + bdnzttar 4*cr2+lt + bdnzttarl 4*cr2+lt + bdzttar 4*cr2+lt + bdzttarl 4*cr2+lt + bttar 4*cr2+lt + bttarl 4*cr2+lt + bttar- 4*cr2+lt + bttarl- 4*cr2+lt + bttar+ 4*cr2+lt + bttarl+ 4*cr2+lt + bctar- 0b01100,4*cr2+eq + bctarl- 0b01100,4*cr2+eq + bctar+ 0b01100,4*cr2+eq + bctarl+ 0b01100,4*cr2+eq + bctar 0b01100,4*cr2+gt + bctar 0b01100,4*cr2+gt,0 + bctar 0b01100,4*cr2+gt,3 + bctarl 0b01100,4*cr2+gt + bctarl 0b01100,4*cr2+gt,0 + bctarl 0b01100,4*cr2+gt,3 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 00ed62c6780..2a44b3ae4c6 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,39 @@ +2019-04-04 Peter Bergner + + PR gas/24349 + * ppc-opc.c (valid_bo_pre_v2): Add comments. + (valid_bo_post_v2): Add support for 'at' branch hints. + (insert_bo): Only error on branch on ctr. + (get_bo_hint_mask): New function. + (insert_boe): Add new 'branch_taken' formal argument. Add support + for inserting 'at' branch hints. + (extract_boe): Add new 'branch_taken' formal argument. Add support + for extracting 'at' branch hints. + (insert_bom, extract_bom, insert_bop, extract_bop): New functions. + (BOE): Delete operand. + (BOM, BOP): New operands. + (RM): Update value. + (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete. + (powerpc_opcodes) : Replace BOE with BOM. + (powerpc_opcodes) : Replace BOE with BOP. + : New extended mnemonics. + 2019-03-28 Alan Modra PR 24390 diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index c4b6c16d337..94ad733b97d 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -321,12 +321,16 @@ valid_bo_pre_v2 (int64_t value) 1z1zz */ if ((value & 0x14) == 0) + /* BO: 0000y, 0001y, 0100y, 0101y. */ return 1; else if ((value & 0x14) == 0x4) + /* BO: 001zy, 011zy. */ return (value & 0x2) == 0; else if ((value & 0x14) == 0x10) + /* BO: 1z00y, 1z01y. */ return (value & 0x8) == 0; else + /* BO: 1z1zz. */ return value == 0x14; } @@ -346,9 +350,17 @@ valid_bo_post_v2 (int64_t value) 1z1zz */ if ((value & 0x14) == 0) + /* BO: 0000z, 0001z, 0100z, 0101z. */ return (value & 0x1) == 0; else if ((value & 0x14) == 0x14) + /* BO: 1z1zz. */ return value == 0x14; + else if ((value & 0x14) == 0x4) + /* BO: 001at, 011at, with "at" == 0b01 being reserved. */ + return (value & 0x3) != 1; + else if ((value & 0x14) == 0x10) + /* BO: 1a00t, 1a01t, with "at" == 0b01 being reserved. */ + return (value & 0x9) != 1; else return 1; } @@ -382,7 +394,8 @@ insert_bo (uint64_t insn, { if (!valid_bo (value, dialect, 0)) *errmsg = _("invalid conditional option"); - else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4)) + else if (PPC_OP (insn) == 19 + && (((insn >> 1) & 0x3ff) == 528) && ! (value & 4)) *errmsg = _("invalid counter access"); return insn | ((value & 0x1f) << 21); } @@ -398,35 +411,128 @@ extract_bo (uint64_t insn, return value; } -/* The BO field in a B form instruction when the + or - modifier is - used. This is like the BO field, but it must be even. When - extracting it, we force it to be even. */ +/* For the given BO value, return a bit mask detailing which bits + define the branch hints. */ + +static int64_t +get_bo_hint_mask (int64_t bo, ppc_cpu_t dialect) +{ + if ((dialect & ISA_V2) == 0) + { + if ((bo & 0x14) != 0x14) + /* BO: 0000y, 0001y, 001zy, 0100y, 0101y, 011zy, 1z00y, 1z01y . */ + return 1; + else + /* BO: 1z1zz. */ + return 0; + } + else + { + if ((bo & 0x14) == 0x4) + /* BO: 001at, 011at. */ + return 0x3; + else if ((bo & 0x14) == 0x10) + /* BO: 1a00t, 1a01t. */ + return 0x9; + else + /* BO: 0000z, 0001z, 0100z, 0101z, 1z1zz. */ + return 0; + } +} + +/* The BO field in a B form instruction when the + or - modifier is used. */ static uint64_t insert_boe (uint64_t insn, int64_t value, ppc_cpu_t dialect, - const char **errmsg) + const char **errmsg, + int branch_taken) { - if (!valid_bo (value, dialect, 0)) - *errmsg = _("invalid conditional option"); - else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4)) - *errmsg = _("invalid counter access"); - else if ((value & 1) != 0) - *errmsg = _("attempt to set y bit when using + or - modifier"); + int64_t implied_hint; + int64_t hint_mask = get_bo_hint_mask (value, dialect); - return insn | ((value & 0x1f) << 21); + if (branch_taken) + implied_hint = hint_mask; + else + implied_hint = hint_mask & ~1; + + /* The branch hint bit(s) in the BO field must either be zero or exactly + match the branch hint bits implied by the '+' or '-' modifier. */ + if (implied_hint == 0) + *errmsg = _("BO value implies no branch hint, when using + or - modifier"); + else if ((value & hint_mask) != 0 + && (value & hint_mask) != implied_hint) + { + if ((dialect & ISA_V2) == 0) + *errmsg = _("attempt to set y bit when using + or - modifier"); + else + *errmsg = _("attempt to set 'at' bits when using + or - modifier"); + } + + value |= implied_hint; + + return insert_bo (insn, value, dialect, errmsg); } static int64_t extract_boe (uint64_t insn, ppc_cpu_t dialect, - int *invalid) + int *invalid, + int branch_taken) { int64_t value = (insn >> 21) & 0x1f; - if (!valid_bo (value, dialect, 1)) + int64_t implied_hint; + int64_t hint_mask = get_bo_hint_mask (value, dialect); + + if (branch_taken) + implied_hint = hint_mask; + else + implied_hint = hint_mask & ~1; + + if (!valid_bo (value, dialect, 1) + || implied_hint == 0 + || (value & hint_mask) != implied_hint) *invalid = 1; - return value & 0x1e; + return value; +} + +/* The BO field in a B form instruction when the - modifier is used. */ + +static uint64_t +insert_bom (uint64_t insn, + int64_t value, + ppc_cpu_t dialect, + const char **errmsg) +{ + return insert_boe (insn, value, dialect, errmsg, 0); +} + +static int64_t +extract_bom (uint64_t insn, + ppc_cpu_t dialect, + int *invalid) +{ + return extract_boe (insn, dialect, invalid, 0); +} + +/* The BO field in a B form instruction when the + modifier is used. */ + +static uint64_t +insert_bop (uint64_t insn, + int64_t value, + ppc_cpu_t dialect, + const char **errmsg) +{ + return insert_boe (insn, value, dialect, errmsg, 1); +} + +static int64_t +extract_bop (uint64_t insn, + ppc_cpu_t dialect, + int *invalid) +{ + return extract_boe (insn, dialect, invalid, 1); } /* The DCMX field in a X form instruction when the field is split @@ -1820,13 +1926,16 @@ const struct powerpc_operand powerpc_operands[] = #define BO_MASK (0x1f << 21) { 0x1f, 21, insert_bo, extract_bo, 0 }, - /* The BO field in a B form instruction when the + or - modifier is - used. This is like the BO field, but it must be even. */ -#define BOE BO + 1 - { 0x1e, 21, insert_boe, extract_boe, 0 }, + /* The BO field in a B form instruction when the - modifier is used. */ +#define BOM BO + 1 + { 0x1f, 21, insert_bom, extract_bom, 0 }, + + /* The BO field in a B form instruction when the + modifier is used. */ +#define BOP BOM + 1 + { 0x1f, 21, insert_bop, extract_bop, 0 }, /* The RM field in an X form instruction. */ -#define RM BOE + 1 +#define RM BOP + 1 #define DD RM { 0x3, 11, NULL, NULL, 0 }, @@ -3259,22 +3368,14 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) (XLLK ((op), (xop), (lk)) | ((((uint64_t)(bo)) & 0x1f) << 21)) #define XLO_MASK (XL_MASK | BO_MASK) -/* An XL form instruction which explicitly sets the y bit of the BO - field. */ -#define XLYLK(op, xop, y, lk) \ - (XLLK ((op), (xop), (lk)) \ - | ((((uint64_t)(y)) & 1) << 21)) -#define XLYLK_MASK (XL_MASK | Y_MASK) - /* An XL form instruction which sets the BO field and the condition bits of the BI field. */ #define XLOCB(op, bo, cb, xop, lk) \ (XLO ((op), (bo), (xop), (lk)) | ((((uint64_t)(cb)) & 3) << 16)) #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1) -/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */ +/* An XL_MASK or XLOCB_MASK with the BB field fixed. */ #define XLBB_MASK (XL_MASK | BB_MASK) -#define XLYBB_MASK (XLYLK_MASK | BB_MASK) #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK) /* A mask for branch instructions using the BH field. */ @@ -4689,17 +4790,17 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}}, {"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}}, -{"bc-", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}}, -{"bc+", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}}, +{"bc-", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOM, BI, BDM}}, +{"bc+", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOP, BI, BDP}}, {"bc", B(16,0,0), B_MASK, COM, PPCVLE, {BO, BI, BD}}, -{"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}}, -{"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}}, +{"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOM, BI, BDM}}, +{"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOP, BI, BDP}}, {"bcl", B(16,0,1), B_MASK, COM, PPCVLE, {BO, BI, BD}}, -{"bca-", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}}, -{"bca+", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}}, +{"bca-", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOM, BI, BDMA}}, +{"bca+", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOP, BI, BDPA}}, {"bca", B(16,1,0), B_MASK, COM, PPCVLE, {BO, BI, BDA}}, -{"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}}, -{"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}}, +{"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOM, BI, BDMA}}, +{"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOP, BI, BDPA}}, {"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}}, {"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}}, @@ -4935,10 +5036,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, {"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, -{"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, -{"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, -{"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, -{"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, +{"bclr-", XLLK(19,16,0), XLBB_MASK, PPCCOM, PPCVLE, {BOM, BI}}, +{"bclrl-", XLLK(19,16,1), XLBB_MASK, PPCCOM, PPCVLE, {BOM, BI}}, +{"bclr+", XLLK(19,16,0), XLBB_MASK, PPCCOM, PPCVLE, {BOP, BI}}, +{"bclrl+", XLLK(19,16,1), XLBB_MASK, PPCCOM, PPCVLE, {BOP, BI}}, {"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, {"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}}, {"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, @@ -5140,19 +5241,131 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, {"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}}, -{"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, -{"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, -{"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, -{"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}}, +{"bcctr-", XLLK(19,528,0), XLBB_MASK, PPCCOM, PPCVLE, {BOM, BI}}, +{"bcctrl-", XLLK(19,528,1), XLBB_MASK, PPCCOM, PPCVLE, {BOM, BI}}, +{"bcctr+", XLLK(19,528,0), XLBB_MASK, PPCCOM, PPCVLE, {BOP, BI}}, +{"bcctrl+", XLLK(19,528,1), XLBB_MASK, PPCCOM, PPCVLE, {BOP, BI}}, {"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, {"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}}, {"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, {"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}}, -{"bctar-", XLYLK(19,560,0,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}}, -{"bctarl-", XLYLK(19,560,0,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}}, -{"bctar+", XLYLK(19,560,1,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}}, -{"bctarl+", XLYLK(19,560,1,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}}, +{"bdnztar", XLO(19,BODNZ,560,0), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, +{"bdnztarl", XLO(19,BODNZ,560,1), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, +{"bdztar", XLO(19,BODZ,560,0), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, +{"bdztarl", XLO(19,BODZ,560,1), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, +{"btar", XLO(19,BOU,560,0), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, +{"btarl", XLO(19,BOU,560,1), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, +{"bdnztar-", XLO(19,BODNZM4,560,0), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, +{"bdnztarl-", XLO(19,BODNZM4,560,1), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, +{"bdnztar+", XLO(19,BODNZP4,560,0), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, +{"bdnztarl+", XLO(19,BODNZP4,560,1), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, +{"bdztar-", XLO(19,BODZM4,560,0), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, +{"bdztarl-", XLO(19,BODZM4,560,1), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, +{"bdztar+", XLO(19,BODZP4,560,0), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, +{"bdztarl+", XLO(19,BODZP4,560,1), XLBOBIBB_MASK, POWER8, PPCVLE, {0}}, + +{"bgetar", XLOCB(19,BOF,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bnltar", XLOCB(19,BOF,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bgetarl", XLOCB(19,BOF,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bnltarl", XLOCB(19,BOF,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bletar", XLOCB(19,BOF,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bngtar", XLOCB(19,BOF,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bletarl", XLOCB(19,BOF,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bngtarl", XLOCB(19,BOF,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bnetar", XLOCB(19,BOF,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bnetarl", XLOCB(19,BOF,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bnstar", XLOCB(19,BOF,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bnutar", XLOCB(19,BOF,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bnstarl", XLOCB(19,BOF,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bnutarl", XLOCB(19,BOF,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bgetar-", XLOCB(19,BOFM4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bnltar-", XLOCB(19,BOFM4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bgetarl-",XLOCB(19,BOFM4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bnltarl-",XLOCB(19,BOFM4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bletar-", XLOCB(19,BOFM4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bngtar-", XLOCB(19,BOFM4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bletarl-",XLOCB(19,BOFM4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bngtarl-",XLOCB(19,BOFM4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bnetar-", XLOCB(19,BOFM4,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bnetarl-",XLOCB(19,BOFM4,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bnstar-", XLOCB(19,BOFM4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bnutar-", XLOCB(19,BOFM4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bnstarl-",XLOCB(19,BOFM4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bnutarl-",XLOCB(19,BOFM4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bgetar+", XLOCB(19,BOFP4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bnltar+", XLOCB(19,BOFP4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bgetarl+",XLOCB(19,BOFP4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bnltarl+",XLOCB(19,BOFP4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bletar+", XLOCB(19,BOFP4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bngtar+", XLOCB(19,BOFP4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bletarl+",XLOCB(19,BOFP4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bngtarl+",XLOCB(19,BOFP4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bnetar+", XLOCB(19,BOFP4,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bnetarl+",XLOCB(19,BOFP4,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bnstar+", XLOCB(19,BOFP4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bnutar+", XLOCB(19,BOFP4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bnstarl+",XLOCB(19,BOFP4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bnutarl+",XLOCB(19,BOFP4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"blttar", XLOCB(19,BOT,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"blttarl", XLOCB(19,BOT,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bgttar", XLOCB(19,BOT,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bgttarl", XLOCB(19,BOT,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"beqtar", XLOCB(19,BOT,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"beqtarl", XLOCB(19,BOT,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bsotar", XLOCB(19,BOT,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"buntar", XLOCB(19,BOT,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bsotarl", XLOCB(19,BOT,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"buntarl", XLOCB(19,BOT,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"blttar-", XLOCB(19,BOTM4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"blttarl-",XLOCB(19,BOTM4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bgttar-", XLOCB(19,BOTM4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bgttarl-",XLOCB(19,BOTM4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"beqtar-", XLOCB(19,BOTM4,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"beqtarl-",XLOCB(19,BOTM4,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bsotar-", XLOCB(19,BOTM4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"buntar-", XLOCB(19,BOTM4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bsotarl-",XLOCB(19,BOTM4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"buntarl-",XLOCB(19,BOTM4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"blttar+", XLOCB(19,BOTP4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"blttarl+",XLOCB(19,BOTP4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bgttar+", XLOCB(19,BOTP4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bgttarl+",XLOCB(19,BOTP4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"beqtar+", XLOCB(19,BOTP4,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"beqtarl+",XLOCB(19,BOTP4,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bsotar+", XLOCB(19,BOTP4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"buntar+", XLOCB(19,BOTP4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"bsotarl+",XLOCB(19,BOTP4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, +{"buntarl+",XLOCB(19,BOTP4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE, {CR}}, + +{"bdnzftar", XLO(19,BODNZF,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, +{"bdnzftarl", XLO(19,BODNZF,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, +{"bdzftar", XLO(19,BODZF,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, +{"bdzftarl", XLO(19,BODZF,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, + +{"bftar", XLO(19,BOF,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, +{"bftarl", XLO(19,BOF,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, +{"bftar-", XLO(19,BOFM4,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, +{"bftarl-", XLO(19,BOFM4,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, +{"bftar+", XLO(19,BOFP4,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, +{"bftarl+", XLO(19,BOFP4,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, + +{"bdnzttar", XLO(19,BODNZT,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, +{"bdnzttarl", XLO(19,BODNZT,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, +{"bdzttar", XLO(19,BODZT,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, +{"bdzttarl", XLO(19,BODZT,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, + +{"bttar", XLO(19,BOT,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, +{"bttarl", XLO(19,BOT,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, +{"bttar-", XLO(19,BOTM4,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, +{"bttarl-", XLO(19,BOTM4,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, +{"bttar+", XLO(19,BOTP4,560,0), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, +{"bttarl+", XLO(19,BOTP4,560,1), XLBOBB_MASK, POWER8, PPCVLE, {BI}}, + +{"bctar-", XLLK(19,560,0), XLBB_MASK, POWER8, PPCVLE, {BOM, BI}}, +{"bctarl-", XLLK(19,560,1), XLBB_MASK, POWER8, PPCVLE, {BOM, BI}}, +{"bctar+", XLLK(19,560,0), XLBB_MASK, POWER8, PPCVLE, {BOP, BI}}, +{"bctarl+", XLLK(19,560,1), XLBB_MASK, POWER8, PPCVLE, {BOP, BI}}, {"bctar", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}}, {"bctarl", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}}, -- 2.30.2