From ab1427f0919bdae2beda2ea11ffa25f6545db233 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 5 Jun 2018 03:55:11 +0100 Subject: [PATCH] add example code --- simple_v_extension/simple_v_chennai_2018.tex | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex index 0d4f43c3d..e3a951273 100644 --- a/simple_v_extension/simple_v_chennai_2018.tex +++ b/simple_v_extension/simple_v_chennai_2018.tex @@ -667,8 +667,8 @@ loop: \begin{itemize} \item Actually about parallelism, not Vectors (or SIMD) per se - \item Only actually needs 3 actual instructions plus CSRs\\ - (RVV - and "standard" SIMD - require ISA duplication) + \item Only needs 3 actual instructions (plus CSRs)\\ + RVV - and "standard" SIMD - require ISA duplication \item Designed for flexibility (graded levels of complexity) \item Huge range of implementor freedom \item Fits RISC-V ethos: achieve more with less -- 2.30.2