From ab14719919d55c1be902c9c723710f1c2c93ecf6 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 6 Mar 2014 18:23:38 -0800 Subject: [PATCH] Add fclass.{s|d} instructions --- riscv/encoding.h | 6 ++++++ riscv/insns/fclass_d.h | 2 ++ riscv/insns/fclass_s.h | 2 ++ softfloat/f32_classify.c | 33 +++++++++++++++++++++++++++++++++ softfloat/f64_classify.c | 33 +++++++++++++++++++++++++++++++++ softfloat/softfloat.h | 2 ++ softfloat/softfloat.mk.in | 2 ++ spike/disasm.cc | 2 ++ 8 files changed, 82 insertions(+) create mode 100644 riscv/insns/fclass_d.h create mode 100644 riscv/insns/fclass_s.h create mode 100755 softfloat/f32_classify.c create mode 100755 softfloat/f64_classify.c diff --git a/riscv/encoding.h b/riscv/encoding.h index 8a4a342..74f72bd 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -145,6 +145,8 @@ #define MASK_SLTIU 0x707f #define MATCH_FADD_S 0x53 #define MASK_FADD_S 0xfe00007f +#define MATCH_FCLASS_D 0xea000053 +#define MASK_FCLASS_D 0xfff0707f #define MATCH_FCVT_S_W 0x70000053 #define MASK_FCVT_S_W 0xfff0007f #define MATCH_MUL 0x2000033 @@ -197,6 +199,8 @@ #define MASK_BLT 0x707f #define MATCH_SCALL 0x73 #define MASK_SCALL 0xffffffff +#define MATCH_FCLASS_S 0xe8000053 +#define MASK_FCLASS_S 0xfff0707f #define MATCH_SC_W 0x1800202f #define MASK_SC_W 0xf800707f #define MATCH_REM 0x2006033 @@ -487,6 +491,7 @@ DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) @@ -513,6 +518,7 @@ DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) DECLARE_INSN(rem, MATCH_REM, MASK_REM) DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) diff --git a/riscv/insns/fclass_d.h b/riscv/insns/fclass_d.h new file mode 100644 index 0000000..bd42d45 --- /dev/null +++ b/riscv/insns/fclass_d.h @@ -0,0 +1,2 @@ +require_fp; +WRITE_RD(f64_classify(FRS1)); diff --git a/riscv/insns/fclass_s.h b/riscv/insns/fclass_s.h new file mode 100644 index 0000000..a010266 --- /dev/null +++ b/riscv/insns/fclass_s.h @@ -0,0 +1,2 @@ +require_fp; +WRITE_RD(f32_classify(FRS1)); diff --git a/softfloat/f32_classify.c b/softfloat/f32_classify.c new file mode 100755 index 0000000..d16aa25 --- /dev/null +++ b/softfloat/f32_classify.c @@ -0,0 +1,33 @@ + +#include +#include +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast16_t f32_classify( float32_t a ) +{ + union ui32_f32 uA; + uint_fast32_t uiA; + + uA.f = a; + uiA = uA.ui; + + uint_fast16_t infOrNaN = expF32UI( uiA ) == 0xFF; + uint_fast16_t subnormalOrZero = expF32UI( uiA ) == 0; + bool sign = signF32UI( uiA ); + + return + ( sign && infOrNaN && fracF32UI( uiA ) == 0 ) << 0 | + ( sign && !infOrNaN && !subnormalOrZero ) << 1 | + ( sign && subnormalOrZero && fracF32UI( uiA ) ) << 2 | + ( sign && subnormalOrZero && fracF32UI( uiA ) == 0 ) << 3 | + ( !sign && infOrNaN && fracF32UI( uiA ) == 0 ) << 7 | + ( !sign && !infOrNaN && !subnormalOrZero ) << 6 | + ( !sign && subnormalOrZero && fracF32UI( uiA ) ) << 5 | + ( !sign && subnormalOrZero && fracF32UI( uiA ) == 0 ) << 4 | + ( isNaNF32UI( uiA ) && softfloat_isSigNaNF32UI( uiA )) << 8 | + ( isNaNF32UI( uiA ) && !softfloat_isSigNaNF32UI( uiA )) << 9; +} + diff --git a/softfloat/f64_classify.c b/softfloat/f64_classify.c new file mode 100755 index 0000000..2ec124b --- /dev/null +++ b/softfloat/f64_classify.c @@ -0,0 +1,33 @@ + +#include +#include +#include "platform.h" +#include "internals.h" +#include "specialize.h" +#include "softfloat.h" + +uint_fast16_t f64_classify( float64_t a ) +{ + union ui64_f64 uA; + uint_fast64_t uiA; + + uA.f = a; + uiA = uA.ui; + + uint_fast16_t infOrNaN = expF64UI( uiA ) == 0x7FF; + uint_fast16_t subnormalOrZero = expF64UI( uiA ) == 0; + bool sign = signF64UI( uiA ); + + return + ( sign && infOrNaN && fracF64UI( uiA ) == 0 ) << 0 | + ( sign && !infOrNaN && !subnormalOrZero ) << 1 | + ( sign && subnormalOrZero && fracF64UI( uiA ) ) << 2 | + ( sign && subnormalOrZero && fracF64UI( uiA ) == 0 ) << 3 | + ( !sign && infOrNaN && fracF64UI( uiA ) == 0 ) << 7 | + ( !sign && !infOrNaN && !subnormalOrZero ) << 6 | + ( !sign && subnormalOrZero && fracF64UI( uiA ) ) << 5 | + ( !sign && subnormalOrZero && fracF64UI( uiA ) == 0 ) << 4 | + ( isNaNF64UI( uiA ) && softfloat_isSigNaNF64UI( uiA )) << 8 | + ( isNaNF64UI( uiA ) && !softfloat_isSigNaNF64UI( uiA )) << 9; +} + diff --git a/softfloat/softfloat.h b/softfloat/softfloat.h index 3eddeed..bacaf1e 100755 --- a/softfloat/softfloat.h +++ b/softfloat/softfloat.h @@ -128,6 +128,7 @@ bool f32_eq_signaling( float32_t, float32_t ); bool f32_le_quiet( float32_t, float32_t ); bool f32_lt_quiet( float32_t, float32_t ); bool f32_isSignalingNaN( float32_t ); +uint_fast16_t f32_classify( float32_t ); /*---------------------------------------------------------------------------- | 64-bit (double-precision) floating-point operations. @@ -158,6 +159,7 @@ bool f64_eq_signaling( float64_t, float64_t ); bool f64_le_quiet( float64_t, float64_t ); bool f64_lt_quiet( float64_t, float64_t ); bool f64_isSignalingNaN( float64_t ); +uint_fast16_t f64_classify( float64_t ); /*---------------------------------------------------------------------------- | Extended double-precision rounding precision. Valid values are 32, 64, and diff --git a/softfloat/softfloat.mk.in b/softfloat/softfloat.mk.in index 2b29f92..7f70053 100644 --- a/softfloat/softfloat.mk.in +++ b/softfloat/softfloat.mk.in @@ -33,6 +33,7 @@ softfloat_c_srcs = \ f32_to_ui32_r_minMag.c \ f32_to_ui64.c \ f32_to_ui64_r_minMag.c \ + f32_classify.c \ f64_add.c \ f64_div.c \ f64_eq.c \ @@ -57,6 +58,7 @@ softfloat_c_srcs = \ f64_to_ui32_r_minMag.c \ f64_to_ui64.c \ f64_to_ui64_r_minMag.c \ + f64_classify.c \ i32_to_f32.c \ i32_to_f64.c \ i64_to_f32.c \ diff --git a/spike/disasm.cc b/spike/disasm.cc index 547b10b..b35c49e 100644 --- a/spike/disasm.cc +++ b/spike/disasm.cc @@ -333,6 +333,7 @@ disassembler_t::disassembler_t() DEFINE_FXTYPE(fcvt_lu_s); DEFINE_FXTYPE(fcvt_w_s); DEFINE_FXTYPE(fcvt_wu_s); + DEFINE_FXTYPE(fclass_s); DEFINE_FXTYPE(fmv_x_s); DEFINE_FXTYPE(feq_s); DEFINE_FXTYPE(flt_s); @@ -363,6 +364,7 @@ disassembler_t::disassembler_t() DEFINE_FXTYPE(fcvt_lu_d); DEFINE_FXTYPE(fcvt_w_d); DEFINE_FXTYPE(fcvt_wu_d); + DEFINE_FXTYPE(fclass_d); DEFINE_FXTYPE(fmv_x_d); DEFINE_FXTYPE(feq_d); DEFINE_FXTYPE(flt_d); -- 2.30.2