From ab1d63a56595f11e10a5326bd83ce84d08badabe Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 9 Aug 2019 17:35:13 -0700
Subject: [PATCH] Check nusers of DSP output, not whole flop

---
 passes/pmgen/xilinx_dsp.pmg | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index f982a10cf..5dee36a11 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -112,8 +112,8 @@ endcode
 match ffP
 	if param(dsp, \PREG).as_int() == 0
 	if !sigPused.empty()
+	if nusers(sigPused) == 2
 	select ffP->type.in($dff)
-	index <int> nusers(port(ffP, \D)) === 2
 	// DSP48E1 does not support clock inversion
 	select param(ffP, \CLK_POLARITY).as_bool()
 	filter param(ffP, \WIDTH).as_int() >= GetSize(sigPused)
-- 
2.30.2