From ab1d746dcedf646029bbbfbb7f85156e8dc63c1e Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Fri, 3 Jul 2015 16:37:26 +0200 Subject: [PATCH] re PR rtl-optimization/66706 (Redundant bitmask instruction on x >> (n & 32)) PR rtl-optimization/66706 * gcc.target/powerpc/shift-int.c: New testcase. From-SVN: r225382 --- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/powerpc/shift-int.c | 23 ++++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/shift-int.c diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 05344971c99..493b730a559 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2015-07-03 Segher Boessenkool + + PR rtl-optimization/66706 + * gcc.target/powerpc/shift-int.c: New testcase. + 2015-07-03 H.J. Lu PR target/66746. diff --git a/gcc/testsuite/gcc.target/powerpc/shift-int.c b/gcc/testsuite/gcc.target/powerpc/shift-int.c new file mode 100644 index 00000000000..fe696ea0d80 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/shift-int.c @@ -0,0 +1,23 @@ +/* Check that shifts do not get unnecessary extends. + See PR66706 for a case where this failed. */ + +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +/* Each function should compile to exactly two instructions. */ +/* { dg-final { scan-assembler-times {(?n)^\s+[a-z]} 16 } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+blr} 8 } } */ + + +typedef unsigned u; +typedef signed s; + +u rot(u x, u n) { return (x << n) | (x >> (32 - n)); } +u shl(u x, u n) { return x << n; } +u shr(u x, u n) { return x >> n; } +s asr(s x, u n) { return x >> n; } + +u roti(u x) { return (x << 23) | (x >> 9); } +u shli(u x) { return x << 23; } +u shri(u x) { return x >> 23; } +s asri(s x) { return x >> 23; } -- 2.30.2