From ab374ae2b8c10fa3361404efe805f5a2f2149c96 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 30 Dec 2022 13:18:21 +0000 Subject: [PATCH] add unit test for Mem class, need to add misaligned ld/st --- src/openpower/decoder/isa/test_mem.py | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 src/openpower/decoder/isa/test_mem.py diff --git a/src/openpower/decoder/isa/test_mem.py b/src/openpower/decoder/isa/test_mem.py new file mode 100644 index 00000000..4436d07f --- /dev/null +++ b/src/openpower/decoder/isa/test_mem.py @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: LGPLv3+ +# Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton +# Funded by NLnet http://nlnet.nl + +import unittest +from openpower.decoder.isa.mem import Mem +from openpower.util import log + + +class TestMem(unittest.TestCase): + + def test_mem_align_ld(self): + m = Mem(row_bytes=8, initial_mem={}) + m.st(4, 0x12345678, width=4, swap=False) + d = m.dump() + log ("dict", d) + self.assertEqual(d, [(0, 0x1234567800000000)]) + + +if __name__ == '__main__': + unittest.main() -- 2.30.2