From ab44857e0045516693abe8aa05dc9bc0bc991d2c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 12 Dec 2021 15:48:37 +0000 Subject: [PATCH] add pretty-print of MMU memory to be used for a TestRunner test --- src/openpower/test/runner.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py index 102d3dd5..57ff2130 100644 --- a/src/openpower/test/runner.py +++ b/src/openpower/test/runner.py @@ -16,6 +16,7 @@ related bugs: from nmigen import Module, ClockSignal from copy import copy +from pprint import pprint # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell # Also, check out the cxxsim nmigen branch, and latest yosys from git @@ -466,6 +467,8 @@ class TestRunnerBase(FHDLTestCase): # optionally, if a wishbone-based ROM is passed in, run that as an # extra emulated process if self.rom is not None: + print ("TestRunner with MMU ROM") + pprint (self.rom) dcache = hdlrun.issuer.core.fus.fus["mmu0"].alu.dcache icache = hdlrun.issuer.core.fus.fus["mmu0"].alu.icache default_mem = self.rom -- 2.30.2