From ab5c6ab9ac98ff18dc27d9e5a71b5d08a513b602 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Mon, 30 Sep 2019 12:56:09 +1000 Subject: [PATCH] fpga: Arty A7's don't need multiple filesets the XDC is identical between variants, so is the fileset Signed-off-by: Benjamin Herrenschmidt --- fpga/{arty_a7-35.xdc => arty_a7.xdc} | 0 microwatt.core | 13 ++++--------- 2 files changed, 4 insertions(+), 9 deletions(-) rename fpga/{arty_a7-35.xdc => arty_a7.xdc} (100%) diff --git a/fpga/arty_a7-35.xdc b/fpga/arty_a7.xdc similarity index 100% rename from fpga/arty_a7-35.xdc rename to fpga/arty_a7.xdc diff --git a/microwatt.core b/microwatt.core index 9604cee..f815c15 100644 --- a/microwatt.core +++ b/microwatt.core @@ -68,14 +68,9 @@ filesets: - fpga/nexys-video.xdc : {file_type : xdc} - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008} - arty_a7-35: - files: - - fpga/arty_a7-35.xdc : {file_type : xdc} - - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008} - - arty_a7-100: + arty_a7: files: - - fpga/arty_a7-35.xdc : {file_type : xdc} + - fpga/arty_a7.xdc : {file_type : xdc} - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008} cmod_a7-35: @@ -102,7 +97,7 @@ targets: arty_a7-35: default_tool: vivado - filesets: [core, arty_a7-35, soc, fpga, debug_xilinx] + filesets: [core, arty_a7, soc, fpga, debug_xilinx] parameters : [memory_size, ram_init_file] tools: vivado: {part : xc7a35ticsg324-1L} @@ -110,7 +105,7 @@ targets: arty_a7-100: default_tool: vivado - filesets: [core, arty_a7-100, soc, fpga, debug_xilinx] + filesets: [core, arty_a7, soc, fpga, debug_xilinx] parameters : [memory_size, ram_init_file] tools: vivado: {part : xc7a100ticsg324-1L} -- 2.30.2