From ab705e77de98d43e68ad691bf8f8e7f02fa98d12 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 6 Jun 2020 05:43:06 +0100 Subject: [PATCH] remove unneeded imports --- src/soc/fu/alu/pipe_data.py | 3 --- src/soc/fu/branch/pipe_data.py | 3 --- src/soc/fu/cr/pipe_data.py | 3 --- src/soc/fu/ldst/pipe_data.py | 5 +---- src/soc/fu/logical/pipe_data.py | 3 --- src/soc/fu/shift_rot/pipe_data.py | 4 ---- src/soc/fu/spr/pipe_data.py | 9 --------- src/soc/fu/trap/pipe_data.py | 10 ---------- 8 files changed, 1 insertion(+), 39 deletions(-) diff --git a/src/soc/fu/alu/pipe_data.py b/src/soc/fu/alu/pipe_data.py index 4039096a..71363049 100644 --- a/src/soc/fu/alu/pipe_data.py +++ b/src/soc/fu/alu/pipe_data.py @@ -1,8 +1,5 @@ -from nmigen import Signal, Const, Cat from soc.fu.alu.alu_input_record import CompALUOpSubset from soc.fu.pipe_data import IntegerData, CommonPipeSpec -from ieee754.fpcommon.getop import FPPipeContext -from soc.decoder.power_decoder2 import Data class ALUInputData(IntegerData): diff --git a/src/soc/fu/branch/pipe_data.py b/src/soc/fu/branch/pipe_data.py index 74edaa1f..1ebfc05b 100644 --- a/src/soc/fu/branch/pipe_data.py +++ b/src/soc/fu/branch/pipe_data.py @@ -23,9 +23,6 @@ op_bctarl CR, TAR, CTR """ -from nmigen import Signal, Const, Cat -from ieee754.fpcommon.getop import FPPipeContext -from soc.decoder.power_decoder2 import Data from soc.fu.pipe_data import IntegerData, CommonPipeSpec from soc.fu.branch.br_input_record import CompBROpSubset # TODO: replace diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py index 00f24dbd..06c7bfb7 100644 --- a/src/soc/fu/cr/pipe_data.py +++ b/src/soc/fu/cr/pipe_data.py @@ -2,11 +2,8 @@ Links: * https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs """ -from nmigen import Signal, Const, Cat -from ieee754.fpcommon.getop import FPPipeContext from soc.fu.pipe_data import IntegerData, CommonPipeSpec from soc.fu.cr.cr_input_record import CompCROpSubset -from soc.decoder.power_decoder2 import Data class CRInputData(IntegerData): diff --git a/src/soc/fu/ldst/pipe_data.py b/src/soc/fu/ldst/pipe_data.py index 063bb5b1..b710a31f 100644 --- a/src/soc/fu/ldst/pipe_data.py +++ b/src/soc/fu/ldst/pipe_data.py @@ -1,8 +1,5 @@ -from nmigen import Signal, Const from soc.fu.alu.alu_input_record import CompLDSTOpSubset -from soc.fu.pipe_data import IntegerData, CommonPipeSpec -from ieee754.fpcommon.getop import FPPipeContext -from soc.decoder.power_decoder2 import Data +from soc.fu.pipe_data import IntegerData class LDSTInputData(IntegerData): diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py index 16cd3f5c..82092b47 100644 --- a/src/soc/fu/logical/pipe_data.py +++ b/src/soc/fu/logical/pipe_data.py @@ -1,7 +1,4 @@ -from nmigen import Signal, Const, Cat -from ieee754.fpcommon.getop import FPPipeContext from soc.fu.pipe_data import IntegerData -from soc.decoder.power_decoder2 import Data from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec from soc.fu.logical.logical_input_record import CompLogicalOpSubset diff --git a/src/soc/fu/shift_rot/pipe_data.py b/src/soc/fu/shift_rot/pipe_data.py index 16f06554..280a7575 100644 --- a/src/soc/fu/shift_rot/pipe_data.py +++ b/src/soc/fu/shift_rot/pipe_data.py @@ -1,10 +1,6 @@ -from nmigen import Signal, Const, Cat -from nmutil.dynamicpipe import SimpleHandshakeRedir from soc.fu.shift_rot.sr_input_record import CompSROpSubset -from ieee754.fpcommon.getop import FPPipeContext from soc.fu.pipe_data import IntegerData, CommonPipeSpec from soc.fu.logical.pipe_data import LogicalOutputData -from nmutil.dynamicpipe import SimpleHandshakeRedir class ShiftRotInputData(IntegerData): diff --git a/src/soc/fu/spr/pipe_data.py b/src/soc/fu/spr/pipe_data.py index 007610af..48439200 100644 --- a/src/soc/fu/spr/pipe_data.py +++ b/src/soc/fu/spr/pipe_data.py @@ -9,10 +9,7 @@ Links: * https://libre-soc.org/openpower/isa/sprset/ """ -from nmigen import Signal, Const -from ieee754.fpcommon.getop import FPPipeContext from soc.fu.pipe_data import IntegerData -from soc.decoder.power_decoder2 import Data from soc.fu.spr.spr_input_record import CompSPROpSubset @@ -43,9 +40,3 @@ class SPROutputData(IntegerData): class SPRPipeSpec: regspec = (SPRInputData.regspec, SPROutputData.regspec) opsubsetkls = CompSPROpSubset - def __init__(self, id_wid, op_wid): - self.id_wid = id_wid - self.op_wid = op_wid - self.opkls = lambda _: self.opsubsetkls(name="op") - self.stage = None - self.pipekls = SimpleHandshakeRedir diff --git a/src/soc/fu/trap/pipe_data.py b/src/soc/fu/trap/pipe_data.py index e0cc881e..6819fb4f 100644 --- a/src/soc/fu/trap/pipe_data.py +++ b/src/soc/fu/trap/pipe_data.py @@ -1,8 +1,4 @@ -from nmigen import Signal, Const -from ieee754.fpcommon.getop import FPPipeContext from soc.fu.pipe_data import IntegerData -from soc.decoder.power_decoder2 import Data -from nmutil.dynamicpipe import SimpleHandshakeRedir from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace @@ -35,9 +31,3 @@ class TrapOutputData(IntegerData): class TrapPipeSpec: regspec = (TrapInputData.regspec, TrapOutputData.regspec) opsubsetkls = CompALUOpSubset - def __init__(self, id_wid, op_wid): - self.id_wid = id_wid - self.op_wid = op_wid - self.opkls = lambda _: self.opsubsetkls(name="op") - self.stage = None - self.pipekls = SimpleHandshakeRedir -- 2.30.2