From ab7b882e47013b56e5bf4281a098c2451ac46137 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 9 Jul 2020 09:45:33 +0100 Subject: [PATCH] add samuel to about us --- about_us.mdwn | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/about_us.mdwn b/about_us.mdwn index a1a29d842..9cd0815f1 100644 --- a/about_us.mdwn +++ b/about_us.mdwn @@ -119,3 +119,22 @@ Alain's website: * Github Profile: [[https://github.com/Sanjay-A-Menon]] * LinkedIn Profile: [[https://www.linkedin.com/in/sanjay-menon-91791815a]] * Availability: ~6hrs/week + +## Samuel Falvo + +* Experience in amateur HDL projects (Kestrel-3 homebrew computer + concept; VDC-II core), Verilog (but not System Verilog), newbie at PCB + design. Extensive experience with test-driven development, Python, RISC-V + assembly language, and Forth. Very comfortable with nMigen, but still + learning things. +* Interests: Forth, Common Lisp, Scheme, assembly language, + {Astro|Semiconductor-}physics, astronomy, martial arts, furry +* Websites: + - https://hackaday.io/project/170581-vdc-ii , + - https://kestrelcomputer.github.io/kestrel/ , + - http://chiselapp.com/user/kc5tja/repository/kestrel-3/index +* Public Repositories: + - https://github.com/sam-falvo , + - https://github.com/kestrelcomputer +* Availability: approximately 20 hrs/wk, circumstances permitting. + -- 2.30.2