From ab827d210d302789db5ae6815aed70989ca43a1b Mon Sep 17 00:00:00 2001 From: "Gabriel L. Somlo" Date: Tue, 18 Jun 2019 16:29:23 -0400 Subject: [PATCH] tools/litex_sim: fix default endianness for mem_init Initializing ROM and/or RAM content requires knowing the CPU endianness before the SimSoC->SoCSDRAM->SoCCore constructor sequence is invoked (before the SoC's self.cpu.endianness could be accessed). Given that the majority of supported CPU models use "little", set it as the new default, and override only for the two models that use "big" endianness. --- litex/tools/litex_sim.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py index 1c0769ae..d97cbb4f 100755 --- a/litex/tools/litex_sim.py +++ b/litex/tools/litex_sim.py @@ -214,10 +214,10 @@ def main(): sim_config = SimConfig(default_clk="sys_clk") sim_config.add_module("serial2console", "serial") - cpu_endianness = "big" + cpu_endianness = "little" if "cpu_type" in soc_kwargs: - if soc_kwargs["cpu_type"] in ["picorv32", "vexriscv"]: - cpu_endianness = "little" + if soc_kwargs["cpu_type"] in ["mor1kx", "lm32"]: + cpu_endianness = "big" if args.rom_init: soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, cpu_endianness) -- 2.30.2