From ab8bbbc1ca08f062ca94d5480b09ff9845834782 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 29 Mar 2022 13:45:51 +0100 Subject: [PATCH] add qspi module to arty_a7 --- src/ls2.py | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/ls2.py b/src/ls2.py index 82186e2..f16425b 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -390,15 +390,16 @@ class DDR3SoC(SoC, Elaboratable): # SPI controller if spi_0_pins is not None and fpga in ['sim', - 'rcs_arctic_tern_bmc_card']: + 'rcs_arctic_tern_bmc_card', + 'arty_a7']: # The Lattice ECP5 devices require special handling on the # dedicated SPI clock line, which is shared with the internal # SPI controller used for FPGA bitstream loading. spi0_is_lattice_ecp5_clk = False - if platform is not None and fpga in ['versa_ecp5', - 'versa_ecp5_85', - 'rcs_arctic_tern_bmc_card', - 'isim']: + if fpga in ['versa_ecp5', + 'versa_ecp5_85', + 'rcs_arctic_tern_bmc_card', + 'isim']: spi0_is_lattice_ecp5_clk = True # Tercel contains two independent Wishbone regions, a @@ -674,6 +675,7 @@ def build_platform(fpga, firmware): spi_0_pins = platform.request("spi_flash_4x", 0, dir={"dq":"io", "cs_n":"o", "clk":"o"}, xdr={"dq": 1, "cs_n": 1, "clk": 0}) + print ("spiflash pins", spi_0_pins) # Get Ethernet RMII resource pins ethmac_0_pins = None -- 2.30.2