From ab8e2090b6435823d50b29b7a255140ba6ea673f Mon Sep 17 00:00:00 2001 From: Nick Clifton Date: Mon, 14 Dec 2009 16:38:23 +0000 Subject: [PATCH] PR binutils/10924 * arm-dis.c (arm_opcodes): Specify %R in cases where using r15 results in unpredictable behaviour. (print_insn_arm): Handle %R. * gas/arm/unpredictable.s: New test case - checks the disassembly of instructions with unpredictable behaviour. * gas/arm/unpredictable.d: New file - expected disassembly. --- gas/testsuite/ChangeLog | 7 ++ gas/testsuite/gas/arm/unpredictable.d | 68 +++++++++++++++++++ gas/testsuite/gas/arm/unpredictable.s | 94 +++++++++++++++++++++++++++ opcodes/ChangeLog | 7 ++ opcodes/arm-dis.c | 69 +++++++++++++------- 5 files changed, 221 insertions(+), 24 deletions(-) create mode 100644 gas/testsuite/gas/arm/unpredictable.d create mode 100644 gas/testsuite/gas/arm/unpredictable.s diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 97983b2f2a4..e8b4372a33b 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2009-12-14 Nick Clifton + + PR binutils/10924 + * gas/arm/unpredictable.s: New test case - checks the disassembly + of instructions with unpredictable behaviour. + * gas/arm/unpredictable.d: New file - expected disassembly. + 2009-12-11 Quentin Neill * gas/i386/fma4.d: Add test cases. diff --git a/gas/testsuite/gas/arm/unpredictable.d b/gas/testsuite/gas/arm/unpredictable.d new file mode 100644 index 00000000000..4b7e801b4e5 --- /dev/null +++ b/gas/testsuite/gas/arm/unpredictable.d @@ -0,0 +1,68 @@ +# name: Upredictable Instructions +# objdump: -D --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]+> [^<]+ +0+004 <[^>]+> [^<]+ +0+008 <[^>]+> [^<]+ +0+00c <[^>]+> [^<]+ +0+010 <[^>]+> [^<]+ +0+014 <[^>]+> [^<]+ +0+018 <[^>]+> [^<]+ +0+01c <[^>]+> [^<]+ +0+020 <[^>]+> [^<]+ +0+024 <[^>]+> [^<]+ +0+028 <[^>]+> [^<]+ +0+02c <[^>]+> [^<]+ +0+030 <[^>]+> [^<]+ +0+034 <[^>]+> [^<]+ +0+038 <[^>]+> [^<]+ +0+03c <[^>]+> [^<]+ +0+040 <[^>]+> [^<]+ +0+044 <[^>]+> [^<]+ +0+048 <[^>]+> [^<]+ +0+04c <[^>]+> [^<]+ +0+050 <[^>]+> [^<]+ +0+054 <[^>]+> [^<]+ +0+058 <[^>]+> [^<]+ +0+05c <[^>]+> [^<]+ +0+060 <[^>]+> [^<]+ +0+064 <[^>]+> [^<]+ +0+068 <[^>]+> [^<]+ +0+06c <[^>]+> [^<]+ +0+070 <[^>]+> [^<]+ +0+074 <[^>]+> [^<]+ +0+078 <[^>]+> [^<]+ +0+07c <[^>]+> [^<]+ +0+080 <[^>]+> [^<]+ +0+084 <[^>]+> [^<]+ +0+088 <[^>]+> [^<]+ +0+08c <[^>]+> [^<]+ +0+090 <[^>]+> [^<]+ +0+094 <[^>]+> [^<]+ +0+098 <[^>]+> [^<]+ +0+09c <[^>]+> [^<]+ +0+0a0 <[^>]+> [^<]+ +0+0a4 <[^>]+> [^<]+ +0+0a8 <[^>]+> [^<]+ +0+0ac <[^>]+> [^<]+ +0+0b0 <[^>]+> [^<]+ +0+0b4 <[^>]+> [^<]+ +0+0b8 <[^>]+> [^<]+ +0+0bc <[^>]+> [^<]+ +0+0c0 <[^>]+> [^<]+ +0+0c4 <[^>]+> [^<]+ +0+0c8 <[^>]+> [^<]+ +0+0cc <[^>]+> [^<]+ +0+0d0 <[^>]+> [^<]+ +0+0d4 <[^>]+> [^<]+ +0+0d8 <[^>]+> [^<]+ +0+0dc <[^>]+> [^<]+ +0+0e0 <[^>]+> [^<]+ +0+0e4 <[^>]+> [^<]+ +0+0e8 <[^>]+> [^<]+ +0+0ec <[^>]+> [^<]+ +#pass + diff --git a/gas/testsuite/gas/arm/unpredictable.s b/gas/testsuite/gas/arm/unpredictable.s new file mode 100644 index 00000000000..36cfce99978 --- /dev/null +++ b/gas/testsuite/gas/arm/unpredictable.s @@ -0,0 +1,94 @@ + .text + .global upredictable +unpredictable: + .word 0x004f00b1 @ strheq r0, [pc], #-1 + .word 0x005fffff @ ldrsheq pc, [pc], #-255 + .word 0x007fffff @ ldrsheq pc, [pc, #-255]! + .word 0x00cf00b0 @ strheq r0, [pc], #0 + .word 0x00df00b0 @ ldrheq r0, [pc], #0 + .word 0x00dfffff @ ldrsheq pc, [pc], #255 + .word 0x00ffffff @ ldrsheq pc, [pc, #255] + .word 0x0000f0b0 @ strheq pc, [r0], -r0 + .word 0x000ff0be @ strheq pc, [pc], -lr + .word 0xe16fff10 @ clz pc, r0 + .word 0xe16f0f1f @ clz r0, r15 + + .word 0xe99f0001 @ ldmib r15, { r0 } + .word 0xe9910000 @ ldmib r1, { } + .word 0xe89f0002 @ ldmia pc, { r1 } + .word 0xe93f0004 @ ldmdb r15!, { r2 } + .word 0xe83f0008 @ ldmda pc!, { r3 } + + ldrb pc, [r0, r1] + ldrbt pc, [r0], r1 + ldrh pc, [r0, r1] + ldrsb pc, [r0, r1] + ldrsb pc, [r0], -r0 + ldrsh pc, [r0, r1] + ldrt pc, [r0], r1 + + .word 0xe020f291 @ mla r0, r1, r2, pc + .word 0xe0202f91 @ mla r0, r1, pc, r2 + .word 0xe020219f @ mla r0, pc, r1, r2 + .word 0xe02f2190 @ mla pc, r0, r1, r2 + @ .word 0xe0202190 @ mla r0, r0, r1, r2 + + mrs pc, cpsr + + mul r0, r1, pc + .word 0xe001009f @ mul r0, pc, r1 + .word 0xe00f0091 @ mul pc, r1, r0 + @ .word 0xe0010091 @ mul r1, r1, r0 + + .word 0xe0e21f93 @ smlal r1, r2, r3, pc + .word 0xe0e2149f @ smlal r1, r2, pc, r4 + .word 0xe0ef1493 @ smlal r1, pc, r3, r4 + .word 0xe0e2f493 @ smlal pc, r2, r3, r4 + @ .word 0xe0e11493 @ smlal r1, r1, r3, r4 + @ .word 0xe0e21492 @ smlal r1, r2, r2, r4 + @ .word 0xe0e21491 @ smlal r1, r2, r1, r4 + + .word 0xe0c21f93 @ smull r1, r2, r3, pc + .word 0xe0c2149f @ smull r1, r2, pc, r4 + .word 0xe0cf1493 @ smull r1, pc, r3, r4 + .word 0xe0c2f493 @ smull pc, r2, r3, r4 + @ .word 0xe0c11493 @ smull r1, r1, r3, r4 + @ .word 0xe0c21492 @ smull r1, r2, r2, r4 + @ .word 0xe0c21491 @ smull r1, r2, r1, r4 + + .word 0xe98f0004 @ stmib r15, { r2 } + .word 0xe88f0008 @ stmia r15, { r3 } + .word 0xe92f0010 @ stmdb r15!, { r4 } + .word 0xe82f0020 @ stmda r15!, { r5 } + + strb pc, [r0, r1] + strbt pc, [r0], r1 + strh pc, [r0, r1] + + .word 0xe103f092 @ swp r15, r2, [r3] + .word 0xe103109f @ swp r1, r15, [r3] + .word 0xe10f1092 @ swp r1, r2, [r15] + @ .word 0xe1031093 @ swp r1, r3, [r3] + @ .word 0xe1033092 @ swp r3, r2, [r3] + + .word 0xe143f092 @ swpb r15, r2, [r3] + .word 0xe143109f @ swpb r1, r15, [r3] + .word 0xe14f1092 @ swpb r1, r2, [r15] + @ .word 0xe1431093 @ swpb r1, r3, [r3] + @ .word 0xe1433092 @ swpb r3, r2, [r3] + + .word 0xe0a21f93 @ umlal r1, r2, r3, r15 + .word 0xe0a2149f @ umlal r1, r2, r15, r4 + .word 0xe0af1493 @ umlal r1, r15, r3, r4 + .word 0xe0a2f493 @ umlal r15, r2, r3, r4 + @ .word 0xe0a11493 @ umlal r1, r1, r3, r4 + @ .word 0xe0a21491 @ umlal r1, r2, r1, r4 + @ .word 0xe0a21492 @ umlal r1, r2, r2, r4 + + .word 0xe0821f93 @ umull r1, r2, r3, r15 + .word 0xe082149f @ umull r1, r2, r15, r4 + .word 0xe08f1493 @ umull r1, r15, r3, r4 + .word 0xe082f493 @ umull r15, r2, r3, r4 + @ .word 0xe0811493 @ umull r1, r1, r3, r4 + @ .word 0xe0821491 @ umull r1, r2, r1, r4 + @ .word 0xe0821492 @ umull r1, r2, r2, r4 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 38bb872d2c9..8e73c91b905 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2009-12-14 Nick Clifton + + PR binutils/10924 + * arm-dis.c (arm_opcodes): Specify %R in cases where using r15 + results in unpredictable behaviour. + (print_insn_arm): Handle %R. + 2009-12-11 H.J. Lu * i386-dis.c (get_valid_dis386): Set vex.w to 0 for VEX C5 diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 88b5cf1c4a2..1f45d5c57f5 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -789,6 +789,7 @@ static const struct opcode32 neon_opcodes[] = %P print address for pli instruction. %r print as an ARM register + %R as %r but r15 is UNPREDICTABLE %d print the bitfield in decimal %W print the bitfield plus one in decimal %x print the bitfield in hex @@ -807,11 +808,11 @@ static const struct opcode32 arm_opcodes[] = /* ARM instructions. */ {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"}, {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, - {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, - {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15r, %0-3r, [%16-19r]"}, - {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, - {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, + {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"}, + {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, + {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15R, %0-3R, [%16-19R]"}, + {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15R, %16-19R, %0-3R, %8-11R"}, + {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15R, %16-19R, %0-3R, %8-11R"}, /* V7 instructions. */ {ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"}, @@ -984,7 +985,7 @@ static const struct opcode32 arm_opcodes[] = {ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"}, {ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"}, {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"}, - {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"}, + {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"}, /* V5E "El Segundo" Instructions. */ {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"}, @@ -1018,18 +1019,23 @@ static const struct opcode32 arm_opcodes[] = /* ARM Instructions. */ {ARM_EXT_V1, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"}, - {ARM_EXT_V1, 0x04000000, 0x0e100000, "str%22'b%t%c\t%12-15r, %a"}, - {ARM_EXT_V1, 0x06000000, 0x0e100ff0, "str%22'b%t%c\t%12-15r, %a"}, - {ARM_EXT_V1, 0x04000000, 0x0c100010, "str%22'b%t%c\t%12-15r, %a"}, - {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%c\t%12-15r, %a"}, - {ARM_EXT_V1, 0x06400000, 0x0e500010, "strb%c\t%12-15r, %a"}, - {ARM_EXT_V1, 0x004000b0, 0x0e5000f0, "strh%c\t%12-15r, %s"}, - {ARM_EXT_V1, 0x000000b0, 0x0e500ff0, "strh%c\t%12-15r, %s"}, + + {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"}, + {ARM_EXT_V1, 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"}, + {ARM_EXT_V1, 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"}, + {ARM_EXT_V1, 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"}, + {ARM_EXT_V1, 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"}, + {ARM_EXT_V1, 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"}, + + {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"}, + {ARM_EXT_V1, 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"}, + {ARM_EXT_V1, 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"}, + {ARM_EXT_V1, 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"}, {ARM_EXT_V1, 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION}, - {ARM_EXT_V1, 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15r, %s"}, + {ARM_EXT_V1, 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"}, {ARM_EXT_V1, 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION}, - {ARM_EXT_V1, 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15r, %s"}, + {ARM_EXT_V1, 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"}, {ARM_EXT_V1, 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"}, {ARM_EXT_V1, 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"}, @@ -1064,7 +1070,7 @@ static const struct opcode32 arm_opcodes[] = {ARM_EXT_V1, 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15r, %16-19r, %o"}, {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"}, - {ARM_EXT_V3, 0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"}, + {ARM_EXT_V3, 0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15R, %22?SCPSR"}, {ARM_EXT_V1, 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"}, {ARM_EXT_V1, 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"}, @@ -1105,13 +1111,18 @@ static const struct opcode32 arm_opcodes[] = {ARM_EXT_V1, 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION}, {ARM_EXT_V1, 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"}, - {ARM_EXT_V1, 0x04100000, 0x0c100000, "ldr%22'b%t%c\t%12-15r, %a"}, + + {ARM_EXT_V1, 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"}, + + {ARM_EXT_V1, 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"}, + {ARM_EXT_V1, 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"}, + {ARM_EXT_V1, 0x092d0000, 0x0fff0000, "push%c\t%m"}, - {ARM_EXT_V1, 0x08800000, 0x0ff00000, "stm%c\t%16-19r%21'!, %m%22'^"}, - {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19r%21'!, %m%22'^"}, + {ARM_EXT_V1, 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"}, + {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, {ARM_EXT_V1, 0x08bd0000, 0x0fff0000, "pop%c\t%m"}, - {ARM_EXT_V1, 0x08900000, 0x0f900000, "ldm%c\t%16-19r%21'!, %m%22'^"}, - {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19r%21'!, %m%22'^"}, + {ARM_EXT_V1, 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"}, + {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"}, @@ -2831,6 +2842,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) || (insn->mask & 0xF0000000) == 0xF0000000 || (insn->mask == 0 && insn->value == 0)) { + bfd_boolean is_unpredictable = FALSE; signed long value_in_comment = 0; const char *c; @@ -2878,7 +2890,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) else { func (stream, "[pc], #%d", offset); - func (stream, UNPREDICTABLE_INSTRUCTION); + is_unpredictable = TRUE; } } else @@ -2937,8 +2949,8 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) if (WRITEBACK_BIT_SET /* Specifying the PC register as the post-indexed registers is also unpredictable. */ - || ((given & 0xf) == 0xf)) - func (stream, UNPREDICTABLE_INSTRUCTION); + || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf))) + is_unpredictable = TRUE; } } } @@ -2972,6 +2984,8 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) func (stream, "%s", arm_regnames[reg]); } func (stream, "}"); + if (! started) + is_unpredictable = TRUE; } break; @@ -3105,6 +3119,10 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) switch (*c) { + case 'R': + if (value == 15) + is_unpredictable = TRUE; + /* Fall through. */ case 'r': func (stream, "%s", arm_regnames[value]); break; @@ -3202,6 +3220,9 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) if (value_in_comment > 32 || value_in_comment < -16) func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL)); + + if (is_unpredictable) + func (stream, UNPREDICTABLE_INSTRUCTION); return; } } -- 2.30.2