From ab9f065c68aa6629f4ce43428a6df8ac318692ae Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Wed, 14 Sep 2022 08:31:34 -0700 Subject: [PATCH] fix some typos --- src/openpower/decoder/isa/test_caller_fptrans.py | 2 +- src/openpower/test/state.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/openpower/decoder/isa/test_caller_fptrans.py b/src/openpower/decoder/isa/test_caller_fptrans.py index 69342a69..384571c3 100644 --- a/src/openpower/decoder/isa/test_caller_fptrans.py +++ b/src/openpower/decoder/isa/test_caller_fptrans.py @@ -8,7 +8,7 @@ from openpower.test.fptrans.fptrans_cases import FPTransCases # writing the test_caller invocation this way makes it work with pytest -class TestSVP64ALU(TestRunnerBase): +class TestFPTrans(TestRunnerBase): def __init__(self, test): assert test == 'test' super().__init__(FPTransCases().test_data, fp=True) diff --git a/src/openpower/test/state.py b/src/openpower/test/state.py index b9165b49..7bc79689 100644 --- a/src/openpower/test/state.py +++ b/src/openpower/test/state.py @@ -188,7 +188,7 @@ class State: class SimState(State): """SimState: Obtains registers and memory from an ISACaller object. - Note that yields are "faked" to maintain consistency and compatability + Note that yields are "faked" to maintain consistency and compatibility within the API. """ def __init__(self, sim): -- 2.30.2