From aba8b16bd123d3d92171c6ab3e472ca55349ca4b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 19 Sep 2022 01:53:35 +0100 Subject: [PATCH] ld/st modes --- openpower/sv/rfc/ls001.mdwn | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 8ae49f789..721e152aa 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -344,22 +344,20 @@ mask `sv.bc/pm=r3`. # LD/ST RM Modes Traditional Vector ISAs have vastly more (and more complex) addressing -modes: unit strided, element strided, Indexed, Structure Packing. All -of these had to be jammed in on top of existing Scalar instructions -**without modifying or adding new Scalar instructions**. -A small conceptual -"cheat" was therefore needed. The Immediate (D) is in some Modes -multiplied by the element index, which gives us element-strided. -For unit-strided the width of the operation (`ld`, 8 byte) is -multiplied by the element index and *substituted* for "D" when -the immediate, D, is zero. Modifications to support this -"cheat" on top of pre-existing Scalar HDL (and Simulators) -have both turned out to be minimal.[^mul] -Also added was the option to perform signed or unsigned Effective -Address calculation, which comes into play only on LD/ST Indexed, -when elwidth overrides are used. Another quirk: `RA` is never -allowed to have its width altered: it remains 64-bit, as it is -the Base Address. +modes than Scalar ISAs: unit strided, element strided, Indexed, Structure +Packing. All of these had to be jammed in on top of existing Scalar +instructions **without modifying or adding new Scalar instructions**. +A small conceptual "cheat" was therefore needed. The Immediate (D) +is in some Modes multiplied by the element index, which gives us +element-strided. For unit-strided the width of the operation (`ld`, +8 byte) is multiplied by the element index and *substituted* for "D" +when the immediate, D, is zero. Modifications to support this "cheat" +on top of pre-existing Scalar HDL (and Simulators) have both turned +out to be minimal.[^mul] Also added was the option to perform signed +or unsigned Effective Address calculation, which comes into play only +on LD/ST Indexed, when elwidth overrides are used. Another quirk: +`RA` is never allowed to have its width altered: it remains 64-bit, +as it is the Base Address. One confusing thing is the unfortunate naming of LD/ST Indexed and REMAP Indexed: some care is taken in the spec to discern the two. -- 2.30.2