From ababd936266a9d89b5e3bd2d9b63ac149c74733b Mon Sep 17 00:00:00 2001 From: Kyrylo Tkachov Date: Tue, 2 Sep 2014 15:57:56 +0000 Subject: [PATCH] [ARM][1/2] Implement lceil, lfloor, lround optabs with new ARMv8-A instructions. PR target/62275 * config/arm/iterators.md (FIXUORS): New code iterator. (VCVT): New int iterator. (su_optab): New code attribute. (su): Likewise. * config/arm/vfp.md (lsi2): New pattern. PR target/62275 * gcc.target/arm/lceil-vcvt_1.c: New test. * gcc.target/arm/lfloor-vcvt_1.c: Likewise. * gcc.target/arm/lround-vcvt_1.c: Likewise. From-SVN: r214825 --- gcc/ChangeLog | 9 +++++++++ gcc/config/arm/iterators.md | 12 +++++++++++ gcc/config/arm/vfp.md | 12 +++++++++++ gcc/testsuite/ChangeLog | 7 +++++++ gcc/testsuite/gcc.target/arm/lceil-vcvt_1.c | 21 ++++++++++++++++++++ gcc/testsuite/gcc.target/arm/lfloor-vcvt_1.c | 21 ++++++++++++++++++++ gcc/testsuite/gcc.target/arm/lround-vcvt_1.c | 21 ++++++++++++++++++++ 7 files changed, 103 insertions(+) create mode 100644 gcc/testsuite/gcc.target/arm/lceil-vcvt_1.c create mode 100644 gcc/testsuite/gcc.target/arm/lfloor-vcvt_1.c create mode 100644 gcc/testsuite/gcc.target/arm/lround-vcvt_1.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 35148ffd927..b46d009219d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2014-09-02 Kyrylo Tkachov + + PR target/62275 + * config/arm/iterators.md (FIXUORS): New code iterator. + (VCVT): New int iterator. + (su_optab): New code attribute. + (su): Likewise. + * config/arm/vfp.md (lsi2): New pattern. + 2014-09-02 Kyrylo Tkachov * config/aarch64/predicates.md (aarch64_comparison_operation): diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 6fe6eef2736..f7e0e1483c9 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -194,6 +194,9 @@ ;; Right shifts (define_code_iterator rshifts [ashiftrt lshiftrt]) +;; Iterator for integer conversions +(define_code_iterator FIXUORS [fix unsigned_fix]) + ;; Binary operators whose second operand can be shifted. (define_code_iterator shiftable_ops [plus minus ior xor and]) @@ -215,6 +218,8 @@ (define_int_iterator VRINT [UNSPEC_VRINTZ UNSPEC_VRINTP UNSPEC_VRINTM UNSPEC_VRINTR UNSPEC_VRINTX UNSPEC_VRINTA]) +(define_int_iterator VCVT [UNSPEC_VRINTP UNSPEC_VRINTM UNSPEC_VRINTA]) + (define_int_iterator NEON_VRINT [UNSPEC_NVRINTP UNSPEC_NVRINTZ UNSPEC_NVRINTM UNSPEC_NVRINTX UNSPEC_NVRINTA UNSPEC_NVRINTN]) @@ -519,6 +524,13 @@ ;; Assembler mnemonics for signedness of widening operations. (define_code_attr US [(sign_extend "s") (zero_extend "u")]) +;; Signedness suffix for float->fixed conversions. Empty for signed +;; conversion. +(define_code_attr su_optab [(fix "") (unsigned_fix "u")]) + +;; Sign prefix to use in instruction type suffixes, i.e. s32, u32. +(define_code_attr su [(fix "s") (unsigned_fix "u")]) + ;; Right shifts (define_code_attr shift [(ashiftrt "ashr") (lshiftrt "lshr")]) (define_code_attr shifttype [(ashiftrt "signed") (lshiftrt "unsigned")]) diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index 005968938f3..3686e1c081a 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -1303,6 +1303,18 @@ (set_attr "conds" "")] ) +;; Implements the lround, lfloor and lceil optabs. +(define_insn "lsi2" + [(set (match_operand:SI 0 "register_operand" "=t") + (FIXUORS:SI (unspec:SDF + [(match_operand:SDF 1 + "register_operand" "")] VCVT)))] + "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 " + "vcvt%?.32.\\t%0, %1" + [(set_attr "predicable" "no") + (set_attr "type" "f_cvtf2i")] +) + ;; MIN_EXPR and MAX_EXPR eventually map to 'smin' and 'smax' in RTL. ;; The 'smax' and 'smin' RTL standard pattern names do not specify which ;; operand will be returned when both operands are zero (i.e. they may not diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0bffdb06ae4..cc340df2d6d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2014-09-02 Kyrylo Tkachov + + PR target/62275 + * gcc.target/arm/lceil-vcvt_1.c: New test. + * gcc.target/arm/lfloor-vcvt_1.c: Likewise. + * gcc.target/arm/lround-vcvt_1.c: Likewise. + 2014-09-02 Paolo Carlini DR 1453 diff --git a/gcc/testsuite/gcc.target/arm/lceil-vcvt_1.c b/gcc/testsuite/gcc.target/arm/lceil-vcvt_1.c new file mode 100644 index 00000000000..bbe42717ad9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/lceil-vcvt_1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2 -march=armv8-a" } */ +/* { dg-add-options arm_v8_vfp } */ + +int +foofloat (float x) +{ + return __builtin_lceilf (x); +} + +/* { dg-final { scan-assembler-times "vcvtp.s32.f32\ts\[0-9\]+, s\[0-9\]+" 1 } } */ + + +int +foodouble (double x) +{ + return __builtin_lceil (x); +} + +/* { dg-final { scan-assembler-times "vcvtp.s32.f64\ts\[0-9\]+, d\[0-9\]+" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/lfloor-vcvt_1.c b/gcc/testsuite/gcc.target/arm/lfloor-vcvt_1.c new file mode 100644 index 00000000000..88671d36960 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/lfloor-vcvt_1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2 -march=armv8-a" } */ +/* { dg-add-options arm_v8_vfp } */ + +int +foofloat (float x) +{ + return __builtin_lfloorf (x); +} + +/* { dg-final { scan-assembler-times "vcvtm.s32.f32\ts\[0-9\]+, s\[0-9\]+" 1 } } */ + + +int +foodouble (double x) +{ + return __builtin_lfloor (x); +} + +/* { dg-final { scan-assembler-times "vcvtm.s32.f64\ts\[0-9\]+, d\[0-9\]+" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/lround-vcvt_1.c b/gcc/testsuite/gcc.target/arm/lround-vcvt_1.c new file mode 100644 index 00000000000..8b1f6a7c3a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/lround-vcvt_1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_vfp_ok } */ +/* { dg-options "-O2 -march=armv8-a -ffast-math" } */ +/* { dg-add-options arm_v8_vfp } */ + +int +foofloat (float x) +{ + return __builtin_lroundf (x); +} + +/* { dg-final { scan-assembler-times "vcvta.s32.f32\ts\[0-9\]+, s\[0-9\]+" 1 } } */ + + +int +foodouble (double x) +{ + return __builtin_lround (x); +} + +/* { dg-final { scan-assembler-times "vcvta.s32.f64\ts\[0-9\]+, d\[0-9\]+" 1 } } */ -- 2.30.2