From abc1c2672e2b2d2ff80b4ccf42027fd629c1ac8b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 20 Feb 2019 16:17:22 -0800 Subject: [PATCH] read_aiger to also rename 0 index lut when wideports --- frontends/aiger/aigerparse.cc | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 5c862b8f0..426e88e53 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -162,9 +162,15 @@ void AigerReader::parse_aiger() int width = wp.second + 1; RTLIL::Wire *wire = module->wire(name); - if (wire) + if (wire) { + RTLIL::Cell* driver = module->cell(stringf("%slut", wire->name.c_str())); + module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0))); + if (driver) + module->rename(driver, stringf("%slut", wire->name.c_str())); + } + // Do not make ports with a mix of input/output into // wide ports bool port_input = false, port_output = false; @@ -408,9 +414,15 @@ void AigerReader::parse_xaiger() int width = wp.second + 1; RTLIL::Wire *wire = module->wire(name); - if (wire) + if (wire) { + RTLIL::Cell* driver = module->cell(stringf("%slut", wire->name.c_str())); + module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0))); + if (driver) + module->rename(driver, stringf("%slut", wire->name.c_str())); + } + // Do not make ports with a mix of input/output into // wide ports bool port_input = false, port_output = false; -- 2.30.2