From abc33f9d61fec2222807284ea4173e6eeff7af5c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 5 Aug 2020 19:13:06 +0100 Subject: [PATCH] clear sel on loadstore --- src/soc/minerva/units/loadstore.py | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/minerva/units/loadstore.py b/src/soc/minerva/units/loadstore.py index ffd6fec4..db05c300 100644 --- a/src/soc/minerva/units/loadstore.py +++ b/src/soc/minerva/units/loadstore.py @@ -85,6 +85,7 @@ class BareLoadStoreUnit(LoadStoreUnitInterface, Elaboratable): m.d.sync += [ self.dbus.cyc.eq(0), self.dbus.stb.eq(0), + self.dbus.sel.eq(0), self.m_ld_data_o.eq(self.dbus.dat_r) ] with m.Elif((self.x_ld_i | self.x_st_i) & -- 2.30.2