From abca85b03479c9d14002396a6453508710259d59 Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Fri, 23 Aug 2019 13:19:11 +0200 Subject: [PATCH] Add constraint file for Nexys A7 --- fpga/nexys_a7.xdc | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 fpga/nexys_a7.xdc diff --git a/fpga/nexys_a7.xdc b/fpga/nexys_a7.xdc new file mode 100644 index 0000000..b94f1bc --- /dev/null +++ b/fpga/nexys_a7.xdc @@ -0,0 +1,7 @@ +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clk] +create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk] + +set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports reset_n] + +set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports uart0_txd] +set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports uart0_rxd] -- 2.30.2