From abe14c0b36180fccb262a6d8531a912b21439925 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 1 Sep 2019 11:44:24 +0100 Subject: [PATCH] add VBLOCK SVP format idea --- simple_v_extension/vblock_format/discussion.mdwn | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/simple_v_extension/vblock_format/discussion.mdwn b/simple_v_extension/vblock_format/discussion.mdwn index 35d0deed1..9fe4a5722 100644 --- a/simple_v_extension/vblock_format/discussion.mdwn +++ b/simple_v_extension/vblock_format/discussion.mdwn @@ -1,7 +1,13 @@ # Alternative (SVPrefix) format This VBLOCK mode effectively extends [[sv_prefix_proposal]] to cover multiple -registers. Its advantage over the main format is that the main format requires +registers. The basic principle: the "prefix" specifies which of source and +destination registers are to be considered "vectors" (or scalars), however +where in SVPrefix that applies to only one instruction, the "vector" tag +designations *continue to cascade* into subsequent instructions within the +VBLOCK. + +Its advantage over the main format is that the main format requires explicit naming of the registers to be tagged (taking up 5 bits each time). | 15 | 14:12 | 11:10 | 9 | 8:7 | 6:0 | -- 2.30.2