From abf47511f57721e791c48852c01bb32d0689525f Mon Sep 17 00:00:00 2001 From: Alan Lawrence Date: Tue, 15 Sep 2015 12:48:15 +0000 Subject: [PATCH] [AArch64 array_mode 6/8] Remove V_TWO_ELEM, again using BLKmode + set_mem_size. * config/aarch64/aarch64-simd.md (aarch64_simd_ld2r): Change operand mode from to BLK. (aarch64_vec_load_lanesoi_lane): Likewise. (aarch64_vec_store_lanesoi_lane): Generate MEM rtx with BLKmode, call set_mem_size. (aarch64_ld2_lane): Likewise. (aarch64_st2_lane): Likewise. * config/aarch64/iterators.md (V_TWO_ELEM): Remove. From-SVN: r227790 --- gcc/ChangeLog | 11 +++++++++++ gcc/config/aarch64/aarch64-simd.md | 20 ++++++++++---------- gcc/config/aarch64/iterators.md | 10 ---------- 3 files changed, 21 insertions(+), 20 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9ba71fe25d4..c1c2c5f1651 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2015-09-15 Alan Lawrence + + * config/aarch64/aarch64-simd.md (aarch64_simd_ld2r): + Change operand mode from to BLK. + (aarch64_vec_load_lanesoi_lane): Likewise. + (aarch64_vec_store_lanesoi_lane): Generate MEM rtx with BLKmode, call set_mem_size. + (aarch64_ld2_lane): Likewise. + (aarch64_st2_lane): Likewise. + * config/aarch64/iterators.md (V_TWO_ELEM): Remove. + 2015-09-15 Alan Lawrence * config/aarch64/aarch64-simd.md (aarch64_simd_ld4r): diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 11b5ded232a..f239ee74226 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3928,7 +3928,7 @@ (define_insn "aarch64_simd_ld2r" [(set (match_operand:OI 0 "register_operand" "=w") - (unspec:OI [(match_operand: 1 "aarch64_simd_struct_operand" "Utv") + (unspec:OI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ] UNSPEC_LD2_DUP))] "TARGET_SIMD" @@ -3938,7 +3938,7 @@ (define_insn "aarch64_vec_load_lanesoi_lane" [(set (match_operand:OI 0 "register_operand" "=w") - (unspec:OI [(match_operand: 1 "aarch64_simd_struct_operand" "Utv") + (unspec:OI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv") (match_operand:OI 2 "register_operand" "0") (match_operand:SI 3 "immediate_operand" "i") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ] @@ -3982,8 +3982,8 @@ ;; RTL uses GCC vector extension indices, so flip only for assembly. (define_insn "aarch64_vec_store_lanesoi_lane" - [(set (match_operand: 0 "aarch64_simd_struct_operand" "=Utv") - (unspec: [(match_operand:OI 1 "register_operand" "w") + [(set (match_operand:BLK 0 "aarch64_simd_struct_operand" "=Utv") + (unspec:BLK [(match_operand:OI 1 "register_operand" "w") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_ST2_LANE))] @@ -4387,8 +4387,8 @@ (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] "TARGET_SIMD" { - machine_mode mode = mode; - rtx mem = gen_rtx_MEM (mode, operands[1]); + rtx mem = gen_rtx_MEM (BLKmode, operands[1]); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 2); emit_insn (gen_aarch64_simd_ld2r (operands[0], mem)); DONE; @@ -4607,8 +4607,8 @@ (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] "TARGET_SIMD" { - machine_mode mode = mode; - rtx mem = gen_rtx_MEM (mode, operands[1]); + rtx mem = gen_rtx_MEM (BLKmode, operands[1]); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 2); emit_insn (gen_aarch64_vec_load_lanesoi_lane (operands[0], mem, @@ -4889,8 +4889,8 @@ (match_operand:SI 2 "immediate_operand")] "TARGET_SIMD" { - machine_mode mode = mode; - rtx mem = gen_rtx_MEM (mode, operands[0]); + rtx mem = gen_rtx_MEM (BLKmode, operands[0]); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (mode)) * 2); emit_insn (gen_aarch64_vec_store_lanesoi_lane (mem, operands[1], diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index c91b354bdec..aab164ad062 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -594,16 +594,6 @@ (V2SI "V16SI") (V2SF "V16SF") (DI "V8DI") (DF "V8DF")]) -;; Mode of pair of elements for each vector mode, to define transfer -;; size for structure lane/dup loads and stores. -(define_mode_attr V_TWO_ELEM [(V8QI "HI") (V16QI "HI") - (V4HI "SI") (V8HI "SI") - (V2SI "V2SI") (V4SI "V2SI") - (DI "V2DI") (V2DI "V2DI") - (V2SF "V2SF") (V4SF "V2SF") - (V4HF "SF") (V8HF "SF") - (DF "V2DI") (V2DF "V2DI")]) - ;; Mode for atomic operation suffixes (define_mode_attr atomic_sfx [(QI "b") (HI "h") (SI "") (DI "")]) -- 2.30.2