From abfd0986a883582e5c607885bad4e17e4ff425cb Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 24 May 2023 12:45:04 +0100 Subject: [PATCH] --- openpower/sv/setvl.mdwn | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn index 0080ee163..e8bcc4449 100644 --- a/openpower/sv/setvl.mdwn +++ b/openpower/sv/setvl.mdwn @@ -166,7 +166,8 @@ loop: ### Loop using Rc=1 In this example, the `setvl.` instruction enabled Rc=1, which -sets CR0.eq when VL becomes zero. +sets CR0.eq when VL becomes zero. Testing of `r4` (cmpi) is thus redundant +saving one instruction. ``` my_fn: @@ -188,7 +189,7 @@ Up to 64 FPRs will be loaded, here. `r3` is set one per bit for each FP register required to be loaded. The block of memory from which the registers are loaded is contiguous (no gaps): any FP register which has a corresponding zero bit in `r3` is *unaltered*. In essence this is a -selective LD-multi with "Scatter" capability. +selective LD-multi with "Scatter" (`VCOMPRESS`) capability. ``` setvli r0, MVL=64, VL=64 -- 2.30.2