From ac0812e00f16f903dd58cff64dd0f0a8dfd0810c Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 5 May 2022 18:49:47 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index b911a67a9..9e55f39a9 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -205,3 +205,14 @@ foundation to take a leap forward in performance and performance/watt, # How do you turn a Scalar ISA into a Vector one? +The most obvious question before that is: why would you want to? +As explained in the "SIMD Considered Harmful" article, Cray-style +Vector ISAs break the link between data element batches and the +underylying architectural back-end parallel processing capability. +Packed SIMD explicitly smashes that width right in the face of the +programmer and expects them to like it. As the article immediately +demonstrates, an arbitrary-sized data set has to contend with +power-of-two setup and teardown that can add literally an order +of magnitude size in the number of hand-written lines of assembler +compared to a well-designed Cray-style Vector ISA with a `setvl` +instruction. -- 2.30.2