From ac309071afe9d28e4635337c1c645a8cfc526a0f Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Tue, 14 Nov 2006 01:13:26 -0500
Subject: [PATCH] Update phase param in the .py file for the cpus

--HG--
extra : convert_revision : cd2eb8c00adcb34b8693a4d1a66187927c0f6803
---
 src/python/m5/objects/BaseCPU.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 2f702a4bf..8037c90af 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -47,6 +47,7 @@ class BaseCPU(SimObject):
         "defer registration with system (for sampling)")
 
     clock = Param.Clock(Parent.clock, "clock speed")
+    phase = Param.Latency("0ns", "clock phase")
 
     _mem_ports = []
 
-- 
2.30.2