From ac45b2ba8c75573b9630656ccf3a20e6da333913 Mon Sep 17 00:00:00 2001 From: Tamar Christina Date: Tue, 30 Aug 2016 15:40:19 +0000 Subject: [PATCH] [PATCH][Aarch64][gcc] Fix vld2/3/4 on big endian systems On behalf of Tamar Christina gcc/ * gcc/config/aarch64/aarch64-simd.md (aarch64_ld2_dreg_le): New. (aarch64_ld2_dreg_be): New. (aarch64_ld2_dreg): Removed. (aarch64_ld3_dreg_le): New. (aarch64_ld3_dreg_be): New. (aarch64_ld3_dreg): Removed. (aarch64_ld4_dreg_le): New. (aarch64_ld4_dreg_be): New. (aarch64_ld4_dreg): Removed. (aarch64_ld): Wrapper around _le, _be. From-SVN: r239865 --- gcc/ChangeLog | 14 +++ gcc/config/aarch64/aarch64-simd.md | 175 ++++++++++++++++++++++++++--- 2 files changed, 173 insertions(+), 16 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 040c6c37f26..c6bda6055fd 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,17 @@ +2016-08-30 Tamar Christina + + * gcc/config/aarch64/aarch64-simd.md + (aarch64_ld2_dreg_le): New. + (aarch64_ld2_dreg_be): New. + (aarch64_ld2_dreg): Removed. + (aarch64_ld3_dreg_le): New. + (aarch64_ld3_dreg_be): New. + (aarch64_ld3_dreg): Removed. + (aarch64_ld4_dreg_le): New. + (aarch64_ld4_dreg_be): New. + (aarch64_ld4_dreg): Removed. + (aarch64_ld): Wrapper around _le, _be. + 2016-08-30 David Malcolm * diagnostic-show-locus.c (test_one_liner_fixit_insert): Remove diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 70140744bb5..f942a54a7ab 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -4901,7 +4901,7 @@ DONE; }) -(define_insn "aarch64_ld2_dreg" +(define_insn "aarch64_ld2_dreg_le" [(set (match_operand:OI 0 "register_operand" "=w") (subreg:OI (vec_concat: @@ -4914,12 +4914,30 @@ (unspec:VD [(match_dup 1)] UNSPEC_LD2) (vec_duplicate:VD (const_int 0)))) 0))] - "TARGET_SIMD" + "TARGET_SIMD && !BYTES_BIG_ENDIAN" + "ld2\\t{%S0. - %T0.}, %1" + [(set_attr "type" "neon_load2_2reg")] +) + +(define_insn "aarch64_ld2_dreg_be" + [(set (match_operand:OI 0 "register_operand" "=w") + (subreg:OI + (vec_concat: + (vec_concat: + (vec_duplicate:VD (const_int 0)) + (unspec:VD + [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")] + UNSPEC_LD2)) + (vec_concat: + (vec_duplicate:VD (const_int 0)) + (unspec:VD [(match_dup 1)] + UNSPEC_LD2))) 0))] + "TARGET_SIMD && BYTES_BIG_ENDIAN" "ld2\\t{%S0. - %T0.}, %1" [(set_attr "type" "neon_load2_2reg")] ) -(define_insn "aarch64_ld2_dreg" +(define_insn "aarch64_ld2_dreg_le" [(set (match_operand:OI 0 "register_operand" "=w") (subreg:OI (vec_concat: @@ -4932,12 +4950,30 @@ (unspec:DX [(match_dup 1)] UNSPEC_LD2) (const_int 0))) 0))] - "TARGET_SIMD" + "TARGET_SIMD && !BYTES_BIG_ENDIAN" "ld1\\t{%S0.1d - %T0.1d}, %1" [(set_attr "type" "neon_load1_2reg")] ) -(define_insn "aarch64_ld3_dreg" +(define_insn "aarch64_ld2_dreg_be" + [(set (match_operand:OI 0 "register_operand" "=w") + (subreg:OI + (vec_concat: + (vec_concat: + (const_int 0) + (unspec:DX + [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")] + UNSPEC_LD2)) + (vec_concat: + (const_int 0) + (unspec:DX [(match_dup 1)] + UNSPEC_LD2))) 0))] + "TARGET_SIMD && BYTES_BIG_ENDIAN" + "ld1\\t{%S0.1d - %T0.1d}, %1" + [(set_attr "type" "neon_load1_2reg")] +) + +(define_insn "aarch64_ld3_dreg_le" [(set (match_operand:CI 0 "register_operand" "=w") (subreg:CI (vec_concat: @@ -4955,12 +4991,35 @@ (unspec:VD [(match_dup 1)] UNSPEC_LD3) (vec_duplicate:VD (const_int 0)))) 0))] - "TARGET_SIMD" + "TARGET_SIMD && !BYTES_BIG_ENDIAN" "ld3\\t{%S0. - %U0.}, %1" [(set_attr "type" "neon_load3_3reg")] ) -(define_insn "aarch64_ld3_dreg" +(define_insn "aarch64_ld3_dreg_be" + [(set (match_operand:CI 0 "register_operand" "=w") + (subreg:CI + (vec_concat: + (vec_concat: + (vec_concat: + (vec_duplicate:VD (const_int 0)) + (unspec:VD + [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")] + UNSPEC_LD3)) + (vec_concat: + (vec_duplicate:VD (const_int 0)) + (unspec:VD [(match_dup 1)] + UNSPEC_LD3))) + (vec_concat: + (vec_duplicate:VD (const_int 0)) + (unspec:VD [(match_dup 1)] + UNSPEC_LD3))) 0))] + "TARGET_SIMD && BYTES_BIG_ENDIAN" + "ld3\\t{%S0. - %U0.}, %1" + [(set_attr "type" "neon_load3_3reg")] +) + +(define_insn "aarch64_ld3_dreg_le" [(set (match_operand:CI 0 "register_operand" "=w") (subreg:CI (vec_concat: @@ -4978,12 +5037,35 @@ (unspec:DX [(match_dup 1)] UNSPEC_LD3) (const_int 0))) 0))] - "TARGET_SIMD" + "TARGET_SIMD && !BYTES_BIG_ENDIAN" + "ld1\\t{%S0.1d - %U0.1d}, %1" + [(set_attr "type" "neon_load1_3reg")] +) + +(define_insn "aarch64_ld3_dreg_be" + [(set (match_operand:CI 0 "register_operand" "=w") + (subreg:CI + (vec_concat: + (vec_concat: + (vec_concat: + (const_int 0) + (unspec:DX + [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")] + UNSPEC_LD3)) + (vec_concat: + (const_int 0) + (unspec:DX [(match_dup 1)] + UNSPEC_LD3))) + (vec_concat: + (const_int 0) + (unspec:DX [(match_dup 1)] + UNSPEC_LD3))) 0))] + "TARGET_SIMD && BYTES_BIG_ENDIAN" "ld1\\t{%S0.1d - %U0.1d}, %1" [(set_attr "type" "neon_load1_3reg")] ) -(define_insn "aarch64_ld4_dreg" +(define_insn "aarch64_ld4_dreg_le" [(set (match_operand:XI 0 "register_operand" "=w") (subreg:XI (vec_concat: @@ -4994,9 +5076,9 @@ UNSPEC_LD4) (vec_duplicate:VD (const_int 0))) (vec_concat: - (unspec:VD [(match_dup 1)] + (unspec:VD [(match_dup 1)] UNSPEC_LD4) - (vec_duplicate:VD (const_int 0)))) + (vec_duplicate:VD (const_int 0)))) (vec_concat: (vec_concat: (unspec:VD [(match_dup 1)] @@ -5006,12 +5088,40 @@ (unspec:VD [(match_dup 1)] UNSPEC_LD4) (vec_duplicate:VD (const_int 0))))) 0))] - "TARGET_SIMD" + "TARGET_SIMD && !BYTES_BIG_ENDIAN" "ld4\\t{%S0. - %V0.}, %1" [(set_attr "type" "neon_load4_4reg")] ) -(define_insn "aarch64_ld4_dreg" +(define_insn "aarch64_ld4_dreg_be" + [(set (match_operand:XI 0 "register_operand" "=w") + (subreg:XI + (vec_concat: + (vec_concat: + (vec_concat: + (vec_duplicate:VD (const_int 0)) + (unspec:VD + [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")] + UNSPEC_LD4)) + (vec_concat: + (vec_duplicate:VD (const_int 0)) + (unspec:VD [(match_dup 1)] + UNSPEC_LD4))) + (vec_concat: + (vec_concat: + (vec_duplicate:VD (const_int 0)) + (unspec:VD [(match_dup 1)] + UNSPEC_LD4)) + (vec_concat: + (vec_duplicate:VD (const_int 0)) + (unspec:VD [(match_dup 1)] + UNSPEC_LD4)))) 0))] + "TARGET_SIMD && BYTES_BIG_ENDIAN" + "ld4\\t{%S0. - %V0.}, %1" + [(set_attr "type" "neon_load4_4reg")] +) + +(define_insn "aarch64_ld4_dreg_le" [(set (match_operand:XI 0 "register_operand" "=w") (subreg:XI (vec_concat: @@ -5024,7 +5134,7 @@ (vec_concat: (unspec:DX [(match_dup 1)] UNSPEC_LD4) - (const_int 0))) + (const_int 0))) (vec_concat: (vec_concat: (unspec:DX [(match_dup 1)] @@ -5034,7 +5144,35 @@ (unspec:DX [(match_dup 1)] UNSPEC_LD4) (const_int 0)))) 0))] - "TARGET_SIMD" + "TARGET_SIMD && !BYTES_BIG_ENDIAN" + "ld1\\t{%S0.1d - %V0.1d}, %1" + [(set_attr "type" "neon_load1_4reg")] +) + +(define_insn "aarch64_ld4_dreg_be" + [(set (match_operand:XI 0 "register_operand" "=w") + (subreg:XI + (vec_concat: + (vec_concat: + (vec_concat: + (const_int 0) + (unspec:DX + [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")] + UNSPEC_LD4)) + (vec_concat: + (const_int 0) + (unspec:DX [(match_dup 1)] + UNSPEC_LD4))) + (vec_concat: + (vec_concat: + (const_int 0) + (unspec:DX [(match_dup 1)] + UNSPEC_LD4)) + (vec_concat: + (const_int 0) + (unspec:DX [(match_dup 1)] + UNSPEC_LD4)))) 0))] + "TARGET_SIMD && BYTES_BIG_ENDIAN" "ld1\\t{%S0.1d - %V0.1d}, %1" [(set_attr "type" "neon_load1_4reg")] ) @@ -5048,7 +5186,12 @@ rtx mem = gen_rtx_MEM (BLKmode, operands[1]); set_mem_size (mem, * 8); - emit_insn (gen_aarch64_ld_dreg (operands[0], mem)); + if (BYTES_BIG_ENDIAN) + emit_insn (gen_aarch64_ld_dreg_be (operands[0], + mem)); + else + emit_insn (gen_aarch64_ld_dreg_le (operands[0], + mem)); DONE; }) -- 2.30.2