From ac498414abc9ed3b6b6ad79343ccc02a63fb5c79 Mon Sep 17 00:00:00 2001 From: whitequark Date: Thu, 13 Dec 2018 13:42:54 +0000 Subject: [PATCH] back.verilog: remove debug code. --- nmigen/back/verilog.py | 1 - 1 file changed, 1 deletion(-) diff --git a/nmigen/back/verilog.py b/nmigen/back/verilog.py index 3eaf07c..c9822c0 100644 --- a/nmigen/back/verilog.py +++ b/nmigen/back/verilog.py @@ -30,7 +30,6 @@ proc_clean write_verilog # Make sure there are no undriven wires in generated RTLIL. proc -write_ilang x.il select -assert-none w:* i:* %a %d o:* %a %ci* %d c:* %co* %a %d n:$* %d """.format(il_text)) if popen.returncode: -- 2.30.2