From ac4d2c60a9f428e90e6d7907707f47c915c3ce6f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 20 Jul 2022 19:35:24 +0100 Subject: [PATCH] add first subvl unit test, subvl comes from RM not SVSTATE --- src/openpower/decoder/isa/caller.py | 18 ++-- .../decoder/isa/test_caller_svp64_subvl.py | 82 +++++++++++++++++++ src/openpower/decoder/power_decoder2.py | 4 +- 3 files changed, 93 insertions(+), 11 deletions(-) create mode 100644 src/openpower/decoder/isa/test_caller_svp64_subvl.py diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index 251a4b28..73fbecf3 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -1298,7 +1298,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): pred_dst_zero = self.pred_dst_zero pred_src_zero = self.pred_src_zero vl = self.svstate.vl - subvl = self.svstate.subvl + subvl = yield self.dec2.rm_dec.rm_in.subvl # VL=0 in SVP64 mode means "do nothing: skip instruction" if self.is_svp64_mode and vl == 0: @@ -1656,12 +1656,12 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): remaps = self.get_remap_indices() remap_idxs = self.remap_idxs vl = self.svstate.vl - subvl = self.svstate.subvl + subvl = yield self.dec2.rm_dec.rm_in.subvl end_sub = substep == subvl end_src = srcstep == vl-1 end_dst = dststep == vl-1 if self.allow_next_step_inc != 2: - self.advance_svstate_steps(end_src, end_dst) + yield from self.advance_svstate_steps(end_src, end_dst) self.namespace['SVSTATE'] = self.svstate.spr # set CR0 (if Rc=1) based on end if rc_en: @@ -1725,7 +1725,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): """ # get SVSTATE VL (oh and print out some debug stuff) vl = self.svstate.vl - subvl = self.svstate.subvl + subvl = yield self.dec2.rm_dec.rm_in.subvl srcstep = self.svstate.srcstep dststep = self.svstate.dststep substep = self.svstate.substep @@ -1821,7 +1821,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): dststep = self.svstate.dststep substep = self.svstate.substep vl = self.svstate.vl - subvl = self.svstate.subvl + subvl = yield self.dec2.rm_dec.rm_in.subvl log(" srcstep", srcstep) log(" dststep", dststep) log(" substep", substep) @@ -1844,7 +1844,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): # this is our Sub-Program-Counter loop from 0 to VL-1 # XXX twin predication TODO vl = self.svstate.vl - subvl = self.svstate.subvl + subvl = yield self.dec2.rm_dec.rm_in.subvl mvl = self.svstate.maxvl srcstep = self.svstate.srcstep dststep = self.svstate.dststep @@ -1856,7 +1856,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): in_vec = not (yield self.dec2.no_in_vec) log(" svstate.vl", vl) log(" svstate.mvl", mvl) - log(" svstate.subvl", subvl) + log(" rm.subvl", subvl) log(" svstate.srcstep", srcstep) log(" svstate.dststep", dststep) log(" svstate.substep", substep) @@ -1882,7 +1882,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): self.update_pc_next() return False if svp64_is_vector and srcstep != vl-1 and dststep != vl-1: - self.advance_svstate_steps() + yield from self.advance_svstate_steps() self.namespace['SVSTATE'] = self.svstate # not an SVP64 branch, so fix PC (NIA==CIA) for next loop # (by default, NIA is CIA+4 if v3.0B or CIA+8 if SVP64) @@ -1900,7 +1900,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): return True def advance_svstate_steps(self, end_src=False, end_dst=False): - subvl = self.svstate.subvl + subvl = yield self.dec2.rm_dec.rm_in.subvl substep = self.svstate.substep end_sub = substep == subvl if end_sub: diff --git a/src/openpower/decoder/isa/test_caller_svp64_subvl.py b/src/openpower/decoder/isa/test_caller_svp64_subvl.py new file mode 100644 index 00000000..f65cd609 --- /dev/null +++ b/src/openpower/decoder/isa/test_caller_svp64_subvl.py @@ -0,0 +1,82 @@ +from nmigen import Module, Signal +from nmigen.sim import Simulator, Delay, Settle +from nmutil.formaltest import FHDLTestCase +import unittest +from openpower.decoder.isa.caller import ISACaller +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.simulator.program import Program +from openpower.decoder.isa.caller import ISACaller, SVP64State, CRFields +from openpower.decoder.selectable_int import SelectableInt +from openpower.decoder.orderedset import OrderedSet +from openpower.decoder.isa.all import ISA +from openpower.decoder.isa.test_caller import Register, run_tst +from openpower.sv.trans.svp64 import SVP64Asm +from openpower.consts import SVP64CROffs +from copy import deepcopy + +class DecoderTestCase(FHDLTestCase): + + def _check_regs(self, sim, expected): + for i in range(32): + self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64)) + + def test_sv_add_intpred(self): + # adds, integer predicated mask r3=0b10 + # 1 = 5 + 9 => not to be touched (skipped) + # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 + # reg num 0 1 2 3 4 5 6 7 8 9 10 11 + # src r3=0b10 N Y N Y + # | | | | + # +-------+ | add + | + # | +-------+ add --+ + # | | + # dest r3=0b10 N Y + isa = SVP64Asm(['sv.add/vec2/m=r30 *1, *5, *9' + ]) + lst = list(isa) + print ("listing", lst) + + # initial values in GPR regfile + initial_regs = [0] * 32 + initial_regs[1] = 0xbeef # not to be altered + initial_regs[2] = 0xefbe # not to be altered + initial_regs[3] = 0xebbe + initial_regs[4] = 0xbeeb + initial_regs[30] = 0b10 # predicate mask + initial_regs[9] = 0x1234 + initial_regs[10] = 0x1111 + initial_regs[11] = 0x7eee + initial_regs[12] = 0x2aaa + initial_regs[5] = 0x4321 + initial_regs[6] = 0x2223 + initial_regs[7] = 0x4321 + initial_regs[8] = 0x2223 + # SVSTATE (in this case, VL=2) + svstate = SVP64State() + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print ("SVSTATE", bin(svstate.asint())) + # copy before running + expected_regs = deepcopy(initial_regs) + expected_regs[1] = 0xbeef + expected_regs[2] = 0x3334 + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, initial_regs, svstate) + self._check_regs(sim, expected_regs) + + + def run_tst_program(self, prog, initial_regs=None, + svstate=None, + initial_cr=0): + if initial_regs is None: + initial_regs = [0] * 32 + simulator = run_tst(prog, initial_regs, svstate=svstate, + initial_cr=initial_cr) + simulator.gpr.dump() + return simulator + + +if __name__ == "__main__": + unittest.main() diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index be218604..15562783 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -1311,7 +1311,7 @@ class PowerDecode2(PowerDecodeSubset): dststep = Signal.like(self.state.svstate.dststep) substep = Signal.like(self.state.svstate.substep) comb += vl.eq(self.state.svstate.vl) - comb += subvl.eq(self.state.svstate.subvl) + comb += subvl.eq(self.rm_dec.rm_in.subvl) comb += srcstep.eq(self.state.svstate.srcstep) comb += dststep.eq(self.state.svstate.dststep) comb += substep.eq(self.state.svstate.substep) @@ -1332,7 +1332,7 @@ class PowerDecode2(PowerDecodeSubset): ("RB", e.read_reg2, dec_b.reg_out, in2_svdec, in2_step, False), ("RC", e.read_reg3, dec_c.reg_out, in3_svdec, in3_step, False), ("RT", e.write_reg, dec_o.reg_out, o_svdec, o_step, True), - ("EA", e.write_ea, dec_o2.reg_out, o2_svdec, o2_step, True))): + ("EA", e.write_ea, dec_o2.reg_out, o2_svdec, o2_step, True))): rname, to_reg, fromreg, svdec, remapstep, out = stuff comb += svdec.extra.eq(extra) # EXTRA field of SVP64 RM comb += svdec.etype.eq(sv_etype) # EXTRA2/3 for this insn -- 2.30.2