From ac4f901154a5cad8f42ecd8d636dedd56b6ef1aa Mon Sep 17 00:00:00 2001 From: Shriya Sharma Date: Wed, 29 Nov 2023 11:19:38 +0000 Subject: [PATCH] Added English language description for addex instruction --- openpower/isa/fixedarith.mdwn | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/openpower/isa/fixedarith.mdwn b/openpower/isa/fixedarith.mdwn index c77c37b8..a8cbbe0e 100644 --- a/openpower/isa/fixedarith.mdwn +++ b/openpower/isa/fixedarith.mdwn @@ -305,6 +305,18 @@ Pseudo-code: if CY=0 then RT <- (RA) + (RB) + OV +Description: + + For CY=0, the sum (RA) + (RB) + OV is placed into regis- + ter RT. + For CY=0, OV is set to 1 if there is a carry out of bit 0 of + the sum in 64-bit mode or there is a carry out of bit 32 + of the sum in 32-bit mode, and set to 0 otherwise. + OV32 is set to 1 if there is a carry out of bit 32 bit of the + sum. + + CY=1, CY=2, and CY=3 are reserved. + Special Registers Altered: OV OV32 (if CY=0 ) -- 2.30.2