From ac842e8b4b85d54b573fcae2c2682c55e513507c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 4 Aug 2020 10:20:15 +0100 Subject: [PATCH] do not use wildcard imports --- src/soc/litex/florent/sim.py | 41 ++++++++++++++++++++++-------------- 1 file changed, 25 insertions(+), 16 deletions(-) diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py index 9e4a5d3f..a24833d8 100755 --- a/src/soc/litex/florent/sim.py +++ b/src/soc/litex/florent/sim.py @@ -1,22 +1,25 @@ #!/usr/bin/env python3 +import os import argparse -from migen import * +from migen import Signal, FSM -from litex.build.generic_platform import * +from litex.build.generic_platform import Pins, Subsignal from litex.build.sim import SimPlatform +from litex.build.io import CRG from litex.build.sim.config import SimConfig -from litex.soc.integration.soc_core import * -from litex.soc.integration.builder import * +from litex.soc.integration.soc import SoCRegion +from litex.soc.integration.soc_core import SoCCore +from litex.soc.integration.builder import Builder from litex.tools.litex_sim import Platform from libresoc import LibreSoC from microwatt import Microwatt -# LibreSoCSim -------------------------------------------------------------------------------------- +# LibreSoCSim ----------------------------------------------------------------- class LibreSoCSim(SoCCore): def __init__(self, cpu="libresoc", debug=False): @@ -24,19 +27,20 @@ class LibreSoCSim(SoCCore): platform = Platform() sys_clk_freq = int(1e6) - # SoCCore ---------------------------------------------------------------------------------- + # SoCCore ------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, cpu_type = "microwatt", - cpu_cls = LibreSoC if cpu == "libresoc" else Microwatt, + cpu_cls = LibreSoC if cpu == "libresoc" \ + else Microwatt, uart_name = "sim", integrated_rom_size = 0x10000, integrated_main_ram_size = 0x10000000) # 256MB self.platform.name = "sim" - # CRG -------------------------------------------------------------------------------------- + # CRG ----------------------------------------------------------------- self.submodules.crg = CRG(platform.request("sys_clk")) - # Debug ------------------------------------------------------------------------------------ + # Debug --------------------------------------------------------------- if debug: uptime = Signal(64) self.sync += uptime.eq(uptime + 1) @@ -71,15 +75,20 @@ class LibreSoCSim(SoCCore): # Stop after 20000 cycles self.sync += If(uptime == 100000, Finish()) -# Build -------------------------------------------------------------------------------------------- +# Build ----------------------------------------------------------------------- def main(): - parser = argparse.ArgumentParser(description="LiteX LibreSoC CPU Simulation") - parser.add_argument("--cpu", default="libresoc", help="CPU to use: libresoc (default) or microwatt") - parser.add_argument("--debug", action="store_true", help="Enable debug traces") - parser.add_argument("--trace", action="store_true", help="Enable tracing") - parser.add_argument("--trace-start", default=0, help="Cycle to start FST tracing") - parser.add_argument("--trace-end", default=-1, help="Cycle to end FST tracing") + parser = argparse.ArgumentParser(description="LiteX LibreSoC CPU Sim") + parser.add_argument("--cpu", default="libresoc", + help="CPU to use: libresoc (default) or microwatt") + parser.add_argument("--debug", action="store_true", + help="Enable debug traces") + parser.add_argument("--trace", action="store_true", + help="Enable tracing") + parser.add_argument("--trace-start", default=0, + help="Cycle to start FST tracing") + parser.add_argument("--trace-end", default=-1, + help="Cycle to end FST tracing") args = parser.parse_args() sim_config = SimConfig(default_clk="sys_clk") -- 2.30.2