From ac8d8783cfcbdc7f2aa300dcc1f4c8adb53d9a5b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 23 Sep 2014 10:21:10 +0200 Subject: [PATCH] k7sataphy: add GTXE2_COMMON instance skeleton --- lib/sata/k7sataphy.py | 71 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 70 insertions(+), 1 deletion(-) diff --git a/lib/sata/k7sataphy.py b/lib/sata/k7sataphy.py index 41e7e204..8c58410d 100644 --- a/lib/sata/k7sataphy.py +++ b/lib/sata/k7sataphy.py @@ -1,6 +1,6 @@ class K7SATAPHY(Module): def __init__(self): - self.specials += [ + self.specials += \ Instance("GTXE2_CHANNEL", # Simulation-Only Attributes p_SIM_RECEIVER_DETECT_PASS=, @@ -657,3 +657,72 @@ class K7SATAPHY(Module): o_TXQPISENN=, o_TXQPISENP= ) + + self.specials += \ + Instance("GTXE2_COMMON", + # Simulation attributes + p_SIM_RESET_SPEEDUP=, + p_SIM_QPLLREFCLK_SEL=, + p_SIM_VERSION=, + + # Common block attributes + p_BIAS_CFG=, + p_COMMON_CFG=, + p_QPLL_CFG=, + p_QPLL_CLKOUT_CFG=, + p_QPLL_COARSE_FREQ_OVRD=, + p_QPLL_COARSE_FREQ_OVRD_EN=, + p_QPLL_CP=, + p_QPLL_CP_MONITOR_EN=, + p_QPLL_DMONITOR_SEL=, + p_QPLL_FBDIV=, + p_QPLL_FBDIV_MONITOR_EN=, + p_QPLL_FBDIV_RATIO=, + p_QPLL_INIT_CFG=, + p_QPLL_LOCK_CFG=, + p_QPLL_LPF=, + p_QPLL_REFCLK_DIV=, + + # Common block - Dynamic Reconfiguration Port (DRP) + i_DRPADDR=, + i_DRPCLK=, + i_DRPDI=, + o_DRPDO=, + i_DRPEN=, + o_DRPRDY=, + i_DRPWE=, + + # Common block - Ref Clock Ports + i_GTGREFCLK=, + i_GTNORTHREFCLK0=, + i_GTNORTHREFCLK1=, + i_GTREFCLK0=, + i_GTREFCLK1=, + i_GTSOUTHREFCLK0=, + i_GTSOUTHREFCLK1=, + + # Common block - QPLL Ports + o_QPLLDMONITOR=, + o_QPLLFBCLKLOST=, + o_QPLLLOCK=, + i_QPLLLOCKDETCLK=, + i_QPLLLOCKEN=, + o_QPLLOUTCLK=, + o_QPLLOUTREFCLK=, + i_QPLLOUTRESET=, + i_QPLLPD=, + o_QPLLREFCLKLOST=, + i_QPLLREFCLKSEL=, + i_QPLLRESET=, + i_QPLLRSVD1=, + i_QPLLRSVD2=, + o_REFCLKOUTMONITOR=, + + # Common block Ports + i_BGBYPASSB=, + i_BGMONITORENB=, + i_BGPDB=, + i_BGRCALOVRD=, + i_PMARSVD=, + i_RCALENB= + ) -- 2.30.2