From ac8f0f721bf0db9ffd0c6602744f1859cb4dd8d2 Mon Sep 17 00:00:00 2001 From: Alan Modra Date: Fri, 7 Apr 2017 18:03:46 +0930 Subject: [PATCH] Remove E6500 insns from PPC_OPCODE_ALTIVEC2 This isn't losing anything from the testsuite. All of these insns appear in testsuite/gas/ppc/e6500.s opcodes/ * ppc-opc.c (powerpc_opcodes ): Enable E6500 only vector instructions with E6500 not PPCVEC2. gas/ * testsuite/gas/ppc/altivec2.s: Delete E6500 vector insns. * testsuite/gas/ppc/altivec2.d: Adjust to suit. --- gas/ChangeLog | 5 + gas/testsuite/gas/ppc/altivec2.d | 182 ++++++++++++------------------- gas/testsuite/gas/ppc/altivec2.s | 48 -------- opcodes/ChangeLog | 8 ++ opcodes/ppc-opc.c | 50 ++++----- 5 files changed, 105 insertions(+), 188 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index 89e94737d73..ff9fca3ed5c 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2017-04-07 Alan Modra + + * testsuite/gas/ppc/altivec2.s: Delete E6500 vector insns. + * testsuite/gas/ppc/altivec2.d: Adjust to suit. + 2017-04-07 Alan Modra * testsuite/gas/elf/section12a.d: Don't expect alignment of 1 diff --git a/gas/testsuite/gas/ppc/altivec2.d b/gas/testsuite/gas/ppc/altivec2.d index 26f9afa9a8c..87a4d1950b9 100644 --- a/gas/testsuite/gas/ppc/altivec2.d +++ b/gas/testsuite/gas/ppc/altivec2.d @@ -7,119 +7,71 @@ Disassembly of section \.text: 0+00 : - 0: (7c 60 e2 0e|0e e2 60 7c) lvepxl v3,0,r28 - 4: (7e 64 92 0e|0e 92 64 7e) lvepxl v19,r4,r18 - 8: (7f 60 9a 4e|4e 9a 60 7f) lvepx v27,0,r19 - c: (7c 39 92 4e|4e 92 39 7c) lvepx v1,r25,r18 - 10: (7f e0 da 0a|0a da e0 7f) lvexbx v31,0,r27 - 14: (7f 81 62 0a|0a 62 81 7f) lvexbx v28,r1,r12 - 18: (7f e0 72 4a|4a 72 e0 7f) lvexhx v31,0,r14 - 1c: (7e 30 fa 4a|4a fa 30 7e) lvexhx v17,r16,r31 - 20: (7e c0 ea 8a|8a ea c0 7e) lvexwx v22,0,r29 - 24: (7e f9 2a 8a|8a 2a f9 7e) lvexwx v23,r25,r5 - 28: (7c 60 66 0a|0a 66 60 7c) lvsm v3,0,r12 - 2c: (7f 7d 0e 0a|0a 0e 7d 7f) lvsm v27,r29,r1 - 30: (7c e0 36 ca|ca 36 e0 7c) lvswxl v7,0,r6 - 34: (7c f0 46 ca|ca 46 f0 7c) lvswxl v7,r16,r8 - 38: (7d c0 94 ca|ca 94 c0 7d) lvswx v14,0,r18 - 3c: (7f 9c 84 ca|ca 84 9c 7f) lvswx v28,r28,r16 - 40: (7f 60 66 8a|8a 66 60 7f) lvtlxl v27,0,r12 - 44: (7f 7c 06 8a|8a 06 7c 7f) lvtlxl v27,r28,r0 - 48: (7e e0 cc 8a|8a cc e0 7e) lvtlx v23,0,r25 - 4c: (7c 39 74 8a|8a 74 39 7c) lvtlx v1,r25,r14 - 50: (7e 80 c6 4a|4a c6 80 7e) lvtrxl v20,0,r24 - 54: (7e dd c6 4a|4a c6 dd 7e) lvtrxl v22,r29,r24 - 58: (7f 00 44 4a|4a 44 00 7f) lvtrx v24,0,r8 - 5c: (7d b7 e4 4a|4a e4 b7 7d) lvtrx v13,r23,r28 - 60: (7d 9c 60 dc|dc 60 9c 7d) mvidsplt v12,r28,r12 - 64: (7d 5b 00 5c|5c 00 5b 7d) mviwsplt v10,r27,r0 - 68: (7f 60 6e 0e|0e 6e 60 7f) stvepxl v27,0,r13 - 6c: (7c 42 fe 0e|0e fe 42 7c) stvepxl v2,r2,r31 - 70: (7c 60 56 4e|4e 56 60 7c) stvepx v3,0,r10 - 74: (7f 7c 06 4e|4e 06 7c 7f) stvepx v27,r28,r0 - 78: (7d a0 33 0a|0a 33 a0 7d) stvexbx v13,0,r6 - 7c: (7d b9 1b 0a|0a 1b b9 7d) stvexbx v13,r25,r3 - 80: (7e c0 0b 4a|4a 0b c0 7e) stvexhx v22,0,r1 - 84: (7e 2e 53 4a|4a 53 2e 7e) stvexhx v17,r14,r10 - 88: (7e a0 db 8a|8a db a0 7e) stvexwx v21,0,r27 - 8c: (7f f2 0b 8a|8a 0b f2 7f) stvexwx v31,r18,r1 - 90: (7f 40 6f 8a|8a 6f 40 7f) stvflxl v26,0,r13 - 94: (7e cd af 8a|8a af cd 7e) stvflxl v22,r13,r21 - 98: (7c a0 4d 8a|8a 4d a0 7c) stvflx v5,0,r9 - 9c: (7e b8 0d 8a|8a 0d b8 7e) stvflx v21,r24,r1 - a0: (7d a0 57 4a|4a 57 a0 7d) stvfrxl v13,0,r10 - a4: (7d b1 cf 4a|4a cf b1 7d) stvfrxl v13,r17,r25 - a8: (7e 20 55 4a|4a 55 20 7e) stvfrx v17,0,r10 - ac: (7d 0c fd 4a|4a fd 0c 7d) stvfrx v8,r12,r31 - b0: (7e 40 ef ca|ca ef 40 7e) stvswxl v18,0,r29 - b4: (7f 4e 47 ca|ca 47 4e 7f) stvswxl v26,r14,r8 - b8: (7c 00 7d ca|ca 7d 00 7c) stvswx v0,0,r15 - bc: (7d b7 3d ca|ca 3d b7 7d) stvswx v13,r23,r7 - c0: (10 d1 84 03|03 84 d1 10) vabsdub v6,v17,v16 - c4: (12 b2 24 43|43 24 b2 12) vabsduh v21,v18,v4 - c8: (13 34 4c 83|83 4c 34 13) vabsduw v25,v20,v9 - cc: (10 d1 a6 ad|ad a6 d1 10) vpermxor v6,v17,v20,v26 - d0: (13 ba 7f 3c|3c 7f ba 13) vaddeuqm v29,v26,v15,v28 - d4: (11 e8 3e 3d|3d 3e e8 11) vaddecuq v15,v8,v7,v24 - d8: (10 46 a8 7e|7e a8 46 10) vsubeuqm v2,v6,v21,v1 - dc: (13 a6 01 3f|3f 01 a6 13) vsubecuq v29,v6,v0,v4 - e0: (11 c9 18 88|88 18 c9 11) vmulouw v14,v9,v3 - e4: (13 10 90 89|89 90 10 13) vmuluwm v24,v16,v18 - e8: (11 51 88 c0|c0 88 51 11) vaddudm v10,v17,v17 - ec: (13 d9 20 c2|c2 20 d9 13) vmaxud v30,v25,v4 - f0: (11 46 e0 c4|c4 e0 46 11) vrld v10,v6,v28 - f4: (13 67 38 c7|c7 38 67 13) vcmpequd v27,v7,v7 - f8: (12 d0 c9 00|00 c9 d0 12) vadduqm v22,v16,v25 - fc: (10 35 e9 40|40 e9 35 10) vaddcuq v1,v21,v29 - 100: (12 8b 99 88|88 99 8b 12) vmulosw v20,v11,v19 - 104: (13 13 09 c2|c2 09 13 13) vmaxsd v24,v19,v1 - 108: (11 bb f2 88|88 f2 bb 11) vmuleuw v13,v27,v30 - 10c: (11 38 8a c2|c2 8a 38 11) vminud v9,v24,v17 - 110: (11 52 e2 c7|c7 e2 52 11) vcmpgtud v10,v18,v28 - 114: (10 1d b3 88|88 b3 1d 10) vmulesw v0,v29,v22 - 118: (11 bc 0b c2|c2 0b bc 11) vminsd v13,v28,v1 - 11c: (11 54 2b c4|c4 2b 54 11) vsrad v10,v20,v5 - 120: (13 75 2b c7|c7 2b 75 13) vcmpgtsd v27,v21,v5 - 124: (10 17 f6 01|01 f6 17 10) bcdadd\. v0,v23,v30,1 - 128: (13 38 d4 08|08 d4 38 13) vpmsumb v25,v24,v26 - 12c: (11 04 26 41|41 26 04 11) bcdsub\. v8,v4,v4,1 - 130: (12 0e d4 48|48 d4 0e 12) vpmsumh v16,v14,v26 - 134: (13 62 d4 4e|4e d4 62 13) vpkudum v27,v2,v26 - 138: (10 d7 8c 88|88 8c d7 10) vpmsumw v6,v23,v17 - 13c: (12 86 cc c8|c8 cc 86 12) vpmsumd v20,v6,v25 - 140: (13 76 84 ce|ce 84 76 13) vpkudus v27,v22,v16 - 144: (12 b4 94 c0|c0 94 b4 12) vsubudm v21,v20,v18 - 148: (12 b4 95 00|00 95 b4 12) vsubuqm v21,v20,v18 - 14c: (13 bd 35 08|08 35 bd 13) vcipher v29,v29,v6 - 150: (10 4d a5 09|09 a5 4d 10) vcipherlast v2,v13,v20 - 154: (12 80 95 0c|0c 95 80 12) vgbbd v20,v18 - 158: (12 68 cd 40|40 cd 68 12) vsubcuq v19,v8,v25 - 15c: (11 3a ed 44|44 ed 3a 11) vorc v9,v26,v29 - 160: (12 94 6d 48|48 6d 94 12) vncipher v20,v20,v13 - 164: (11 e5 dd 49|49 dd e5 11) vncipherlast v15,v5,v27 - 168: (10 73 35 4c|4c 35 73 10) vbpermq v3,v19,v6 - 16c: (13 c4 e5 4e|4e e5 c4 13) vpksdus v30,v4,v28 - 170: (10 04 75 84|84 75 04 10) vnand v0,v4,v14 - 174: (12 28 ed c4|c4 ed 28 12) vsld v17,v8,v29 - 178: (13 b4 05 c8|c8 05 b4 13) vsbox v29,v20 - 17c: (11 67 5d ce|ce 5d 67 11) vpksdss v11,v7,v11 - 180: (10 73 84 c7|c7 84 73 10) vcmpequd\. v3,v19,v16 - 184: (12 40 8e 4e|4e 8e 40 12) vupkhsw v18,v17 - 188: (13 a8 6e 82|82 6e a8 13) vshasigmaw v29,v8,0,13 - 18c: (12 fc d6 84|84 d6 fc 12) veqv v23,v28,v26 - 190: (13 a0 17 8c|8c 17 a0 13) vmrgew v29,v0,v2 - 194: (13 a0 16 8c|8c 16 a0 13) vmrgow v29,v0,v2 - 198: (13 73 06 c2|c2 06 73 13) vshasigmad v27,v19,0,0 - 19c: (12 9c e6 c4|c4 e6 9c 12) vsrd v20,v28,v28 - 1a0: (12 40 ae ce|ce ae 40 12) vupklsw v18,v21 - 1a4: (13 c0 3f 02|02 3f c0 13) vclzb v30,v7 - 1a8: (13 a0 af 03|03 af a0 13) vpopcntb v29,v21 - 1ac: (13 20 af 42|42 af 20 13) vclzh v25,v21 - 1b0: (12 00 f7 43|43 f7 00 12) vpopcnth v16,v30 - 1b4: (13 80 1f 82|82 1f 80 13) vclzw v28,v3 - 1b8: (11 40 4f 83|83 4f 40 11) vpopcntw v10,v9 - 1bc: (12 c0 4f c2|c2 4f c0 12) vclzd v22,v9 - 1c0: (11 e0 f7 c3|c3 f7 e0 11) vpopcntd v15,v30 - 1c4: (10 5f 36 c7|c7 36 5f 10) vcmpgtud\. v2,v31,v6 - 1c8: (12 8f 17 c7|c7 17 8f 12) vcmpgtsd\. v20,v15,v2 +.*: (10 d1 84 03|03 84 d1 10) vabsdub v6,v17,v16 +.*: (12 b2 24 43|43 24 b2 12) vabsduh v21,v18,v4 +.*: (13 34 4c 83|83 4c 34 13) vabsduw v25,v20,v9 +.*: (10 d1 a6 ad|ad a6 d1 10) vpermxor v6,v17,v20,v26 +.*: (13 ba 7f 3c|3c 7f ba 13) vaddeuqm v29,v26,v15,v28 +.*: (11 e8 3e 3d|3d 3e e8 11) vaddecuq v15,v8,v7,v24 +.*: (10 46 a8 7e|7e a8 46 10) vsubeuqm v2,v6,v21,v1 +.*: (13 a6 01 3f|3f 01 a6 13) vsubecuq v29,v6,v0,v4 +.*: (11 c9 18 88|88 18 c9 11) vmulouw v14,v9,v3 +.*: (13 10 90 89|89 90 10 13) vmuluwm v24,v16,v18 +.*: (11 51 88 c0|c0 88 51 11) vaddudm v10,v17,v17 +.*: (13 d9 20 c2|c2 20 d9 13) vmaxud v30,v25,v4 +.*: (11 46 e0 c4|c4 e0 46 11) vrld v10,v6,v28 +.*: (13 67 38 c7|c7 38 67 13) vcmpequd v27,v7,v7 +.*: (12 d0 c9 00|00 c9 d0 12) vadduqm v22,v16,v25 +.*: (10 35 e9 40|40 e9 35 10) vaddcuq v1,v21,v29 +.*: (12 8b 99 88|88 99 8b 12) vmulosw v20,v11,v19 +.*: (13 13 09 c2|c2 09 13 13) vmaxsd v24,v19,v1 +.*: (11 bb f2 88|88 f2 bb 11) vmuleuw v13,v27,v30 +.*: (11 38 8a c2|c2 8a 38 11) vminud v9,v24,v17 +.*: (11 52 e2 c7|c7 e2 52 11) vcmpgtud v10,v18,v28 +.*: (10 1d b3 88|88 b3 1d 10) vmulesw v0,v29,v22 +.*: (11 bc 0b c2|c2 0b bc 11) vminsd v13,v28,v1 +.*: (11 54 2b c4|c4 2b 54 11) vsrad v10,v20,v5 +.*: (13 75 2b c7|c7 2b 75 13) vcmpgtsd v27,v21,v5 +.*: (10 17 f6 01|01 f6 17 10) bcdadd\. v0,v23,v30,1 +.*: (13 38 d4 08|08 d4 38 13) vpmsumb v25,v24,v26 +.*: (11 04 26 41|41 26 04 11) bcdsub\. v8,v4,v4,1 +.*: (12 0e d4 48|48 d4 0e 12) vpmsumh v16,v14,v26 +.*: (13 62 d4 4e|4e d4 62 13) vpkudum v27,v2,v26 +.*: (10 d7 8c 88|88 8c d7 10) vpmsumw v6,v23,v17 +.*: (12 86 cc c8|c8 cc 86 12) vpmsumd v20,v6,v25 +.*: (13 76 84 ce|ce 84 76 13) vpkudus v27,v22,v16 +.*: (12 b4 94 c0|c0 94 b4 12) vsubudm v21,v20,v18 +.*: (12 b4 95 00|00 95 b4 12) vsubuqm v21,v20,v18 +.*: (13 bd 35 08|08 35 bd 13) vcipher v29,v29,v6 +.*: (10 4d a5 09|09 a5 4d 10) vcipherlast v2,v13,v20 +.*: (12 80 95 0c|0c 95 80 12) vgbbd v20,v18 +.*: (12 68 cd 40|40 cd 68 12) vsubcuq v19,v8,v25 +.*: (11 3a ed 44|44 ed 3a 11) vorc v9,v26,v29 +.*: (12 94 6d 48|48 6d 94 12) vncipher v20,v20,v13 +.*: (11 e5 dd 49|49 dd e5 11) vncipherlast v15,v5,v27 +.*: (10 73 35 4c|4c 35 73 10) vbpermq v3,v19,v6 +.*: (13 c4 e5 4e|4e e5 c4 13) vpksdus v30,v4,v28 +.*: (10 04 75 84|84 75 04 10) vnand v0,v4,v14 +.*: (12 28 ed c4|c4 ed 28 12) vsld v17,v8,v29 +.*: (13 b4 05 c8|c8 05 b4 13) vsbox v29,v20 +.*: (11 67 5d ce|ce 5d 67 11) vpksdss v11,v7,v11 +.*: (10 73 84 c7|c7 84 73 10) vcmpequd\. v3,v19,v16 +.*: (12 40 8e 4e|4e 8e 40 12) vupkhsw v18,v17 +.*: (13 a8 6e 82|82 6e a8 13) vshasigmaw v29,v8,0,13 +.*: (12 fc d6 84|84 d6 fc 12) veqv v23,v28,v26 +.*: (13 a0 17 8c|8c 17 a0 13) vmrgew v29,v0,v2 +.*: (13 a0 16 8c|8c 16 a0 13) vmrgow v29,v0,v2 +.*: (13 73 06 c2|c2 06 73 13) vshasigmad v27,v19,0,0 +.*: (12 9c e6 c4|c4 e6 9c 12) vsrd v20,v28,v28 +.*: (12 40 ae ce|ce ae 40 12) vupklsw v18,v21 +.*: (13 c0 3f 02|02 3f c0 13) vclzb v30,v7 +.*: (13 a0 af 03|03 af a0 13) vpopcntb v29,v21 +.*: (13 20 af 42|42 af 20 13) vclzh v25,v21 +.*: (12 00 f7 43|43 f7 00 12) vpopcnth v16,v30 +.*: (13 80 1f 82|82 1f 80 13) vclzw v28,v3 +.*: (11 40 4f 83|83 4f 40 11) vpopcntw v10,v9 +.*: (12 c0 4f c2|c2 4f c0 12) vclzd v22,v9 +.*: (11 e0 f7 c3|c3 f7 e0 11) vpopcntd v15,v30 +.*: (10 5f 36 c7|c7 36 5f 10) vcmpgtud\. v2,v31,v6 +.*: (12 8f 17 c7|c7 17 8f 12) vcmpgtsd\. v20,v15,v2 #pass diff --git a/gas/testsuite/gas/ppc/altivec2.s b/gas/testsuite/gas/ppc/altivec2.s index 6233c0e52ef..89b9b1f3d73 100644 --- a/gas/testsuite/gas/ppc/altivec2.s +++ b/gas/testsuite/gas/ppc/altivec2.s @@ -1,53 +1,5 @@ .text start: - lvepxl 3,0,28 - lvepxl 19,4,18 - lvepx 27,0,19 - lvepx 1,25,18 - lvexbx 31,0,27 - lvexbx 28,1,12 - lvexhx 31,0,14 - lvexhx 17,16,31 - lvexwx 22,0,29 - lvexwx 23,25,5 - lvsm 3,0,12 - lvsm 27,29,1 - lvswxl 7,0,6 - lvswxl 7,16,8 - lvswx 14,0,18 - lvswx 28,28,16 - lvtlxl 27,0,12 - lvtlxl 27,28,0 - lvtlx 23,0,25 - lvtlx 1,25,14 - lvtrxl 20,0,24 - lvtrxl 22,29,24 - lvtrx 24,0,8 - lvtrx 13,23,28 - mvidsplt 12,28,12 - mviwsplt 10,27,0 - stvepxl 27,0,13 - stvepxl 2,2,31 - stvepx 3,0,10 - stvepx 27,28,0 - stvexbx 13,0,6 - stvexbx 13,25,3 - stvexhx 22,0,1 - stvexhx 17,14,10 - stvexwx 21,0,27 - stvexwx 31,18,1 - stvflxl 26,0,13 - stvflxl 22,13,21 - stvflx 5,0,9 - stvflx 21,24,1 - stvfrxl 13,0,10 - stvfrxl 13,17,25 - stvfrx 17,0,10 - stvfrx 8,12,31 - stvswxl 18,0,29 - stvswxl 26,14,8 - stvswx 0,0,15 - stvswx 13,23,7 vabsdub 6,17,16 vabsduh 21,18,4 vabsduw 25,20,9 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 424d7fc12c9..73a0071a938 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,11 @@ +2017-04-07 Alan Modra + + * ppc-opc.c (powerpc_opcodes ): Enable E6500 only + vector instructions with E6500 not PPCVEC2. + 2017-04-06 Pip Cet * Makefile.am: Add wasm32-dis.c. diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 7e9f9f41480..e48d664e30b 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -4892,7 +4892,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, {"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, -{"mviwsplt", X(31,46), X_MASK, PPCVEC2, 0, {VD, RA, RB}}, +{"mviwsplt", X(31,46), X_MASK, E6500, 0, {VD, RA, RB}}, {"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, @@ -4988,7 +4988,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, {"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, -{"mvidsplt", X(31,110), X_MASK, PPCVEC2, 0, {VD, RA, RB}}, +{"mvidsplt", X(31,110), X_MASK, E6500, 0, {VD, RA, RB}}, {"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}}, @@ -5188,11 +5188,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}}, {"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}}, -{"lvexbx", X(31,261), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, +{"lvexbx", X(31,261), X_MASK, E6500, 0, {VD, RA0, RB}}, {"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}}, -{"lvepxl", X(31,263), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, +{"lvepxl", X(31,263), X_MASK, E6500, 0, {VD, RA0, RB}}, {"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, {"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, @@ -5238,8 +5238,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfdcrux", X(31,291), X_MASK, PPC464, 0, {RS, RA}}, -{"lvexhx", X(31,293), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, -{"lvepx", X(31,295), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, +{"lvexhx", X(31,293), X_MASK, E6500, 0, {VD, RA0, RB}}, +{"lvepx", X(31,295), X_MASK, E6500, 0, {VD, RA0, RB}}, {"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, @@ -5302,7 +5302,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}}, {"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}}, -{"lvexwx", X(31,325), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, +{"lvexwx", X(31,325), X_MASK, E6500, 0, {VD, RA0, RB}}, {"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}}, @@ -5551,7 +5551,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}}, {"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}}, -{"stvexbx", X(31,389), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, +{"stvexbx", X(31,389), X_MASK, E6500, 0, {VS, RA0, RB}}, {"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, {"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, @@ -5584,7 +5584,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtdcrux", X(31,419), X_MASK, PPC464, 0, {RA, RS}}, -{"stvexhx", X(31,421), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, +{"stvexhx", X(31,421), X_MASK, E6500, 0, {VS, RA0, RB}}, {"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}}, @@ -5656,7 +5656,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}}, {"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}}, -{"stvexwx", X(31,453), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, +{"stvexwx", X(31,453), X_MASK, E6500, 0, {VS, RA0, RB}}, {"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}}, {"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, 0, {CT}}, @@ -5927,7 +5927,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}}, {"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}}, -{"lvtrx", X(31,549), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, +{"lvtrx", X(31,549), X_MASK, E6500, 0, {VD, RA0, RB}}, {"bbelr", X(31,550), X_MASK, PPCBRLK, 0, {0}}, @@ -5951,7 +5951,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}}, {"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}}, -{"lvtlx", X(31,581), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, +{"lvtlx", X(31,581), X_MASK, E6500, 0, {VD, RA0, RB}}, {"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}}, @@ -5981,7 +5981,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}}, -{"lvswx", X(31,613), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, +{"lvswx", X(31,613), X_MASK, E6500, 0, {VD, RA0, RB}}, {"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}}, @@ -6040,7 +6040,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}}, {"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}}, -{"stvfrx", X(31,677), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, +{"stvfrx", X(31,677), X_MASK, E6500, 0, {VS, RA0, RB}}, {"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}}, {"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, @@ -6058,7 +6058,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}}, {"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}}, -{"stvflx", X(31,709), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, +{"stvflx", X(31,709), X_MASK, E6500, 0, {VS, RA0, RB}}, {"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}}, @@ -6096,7 +6096,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}}, -{"stvswx", X(31,741), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, +{"stvswx", X(31,741), X_MASK, E6500, 0, {VS, RA0, RB}}, {"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}}, @@ -6134,11 +6134,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}}, {"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}}, -{"lvsm", X(31,773), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, +{"lvsm", X(31,773), X_MASK, E6500, 0, {VD, RA0, RB}}, {"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}}, -{"stvepxl", X(31,775), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, +{"stvepxl", X(31,775), X_MASK, E6500, 0, {VS, RA0, RB}}, {"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}}, {"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, @@ -6177,8 +6177,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}}, -{"lvtrxl", X(31,805), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, -{"stvepx", X(31,807), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, +{"lvtrxl", X(31,805), X_MASK, E6500, 0, {VD, RA0, RB}}, +{"stvepx", X(31,807), X_MASK, E6500, 0, {VS, RA0, RB}}, {"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}}, {"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, @@ -6204,7 +6204,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}}, {"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}}, -{"lvtlxl", X(31,837), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, +{"lvtlxl", X(31,837), X_MASK, E6500, 0, {VD, RA0, RB}}, {"cpabort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}}, @@ -6231,7 +6231,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}}, -{"lvswxl", X(31,869), X_MASK, PPCVEC2, 0, {VD, RA0, RB}}, +{"lvswxl", X(31,869), X_MASK, E6500, 0, {VD, RA0, RB}}, {"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}}, {"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}}, @@ -6295,7 +6295,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}}, -{"stvfrxl", X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, +{"stvfrxl", X(31,933), X_MASK, E6500, 0, {VS, RA0, RB}}, {"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}}, {"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L2}}, @@ -6330,7 +6330,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}}, {"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}}, -{"stvflxl", X(31,965), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, +{"stvflxl", X(31,965), X_MASK, E6500, 0, {VS, RA0, RB}}, {"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}}, {"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, 0, {CT}}, @@ -6362,7 +6362,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, -{"stvswxl", X(31,997), X_MASK, PPCVEC2, 0, {VS, RA0, RB}}, +{"stvswxl", X(31,997), X_MASK, E6500, 0, {VS, RA0, RB}}, {"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}}, -- 2.30.2