From aca00c0645d2b5f1c22677281549ee80d3c84561 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Tiago=20M=C3=BCck?= Date: Fri, 12 Jul 2019 17:35:33 -0500 Subject: [PATCH] arch-arm: Using acquire/release memory flags MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Appends the acquire/release memory flags for the instructions with those semantics. Change-Id: I9d1e12c6ced511f2ff7a1006c27ae9014965e044 Signed-off-by: Tiago Mück Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27133 Tested-by: kokoro Maintainer: Giacomo Travaglini Reviewed-by: Anthony Gutierrez --- src/arch/arm/isa/insts/ldr.isa | 4 +++- src/arch/arm/isa/insts/ldr64.isa | 4 +++- src/arch/arm/isa/insts/str.isa | 4 +++- src/arch/arm/isa/insts/str64.isa | 4 +++- 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa index dc1d65021..d828fcff0 100644 --- a/src/arch/arm/isa/insts/ldr.isa +++ b/src/arch/arm/isa/insts/ldr.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010-2011,2019 ARM Limited +// Copyright (c) 2010-2011,2019-2020 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -182,6 +182,7 @@ let {{ self.instFlags.extend(["IsMemBarrier", "IsWriteBarrier", "IsReadBarrier"]) + self.memFlags.append("Request::ACQUIRE") # Disambiguate the class name for different flavors of loads if self.flavor != "normal": @@ -256,6 +257,7 @@ let {{ self.instFlags.extend(["IsMemBarrier", "IsWriteBarrier", "IsReadBarrier"]) + self.memFlags.append("Request::ACQUIRE") def emit(self): # Address computation code diff --git a/src/arch/arm/isa/insts/ldr64.isa b/src/arch/arm/isa/insts/ldr64.isa index 4f1250938..fc4f34f0c 100644 --- a/src/arch/arm/isa/insts/ldr64.isa +++ b/src/arch/arm/isa/insts/ldr64.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2011-2014, 2017, 2019 ARM Limited +// Copyright (c) 2011-2014, 2017, 2019-2020 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -94,6 +94,8 @@ let {{ self.instFlags.extend(["IsMemBarrier", "IsWriteBarrier", "IsReadBarrier"]) + self.memFlags.append("Request::ACQUIRE") + if self.flavor in ("acex", "exclusive", "exp", "acexp"): self.memFlags.append("Request::LLSC") diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa index f5424789c..e99f6adc4 100644 --- a/src/arch/arm/isa/insts/str.isa +++ b/src/arch/arm/isa/insts/str.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010-2011,2017,2019 ARM Limited +// Copyright (c) 2010-2011,2017,2019-2020 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -190,6 +190,7 @@ let {{ self.instFlags.extend(["IsMemBarrier", "IsWriteBarrier", "IsReadBarrier"]) + self.memFlags.append("Request::RELEASE") # Disambiguate the class name for different flavors of stores if self.flavor != "normal": @@ -271,6 +272,7 @@ let {{ self.instFlags.extend(["IsMemBarrier", "IsWriteBarrier", "IsReadBarrier"]) + self.memFlags.append("Request::RELEASE") # Disambiguate the class name for different flavors of stores if self.flavor != "normal": diff --git a/src/arch/arm/isa/insts/str64.isa b/src/arch/arm/isa/insts/str64.isa index 22d145661..7ad1cad2c 100644 --- a/src/arch/arm/isa/insts/str64.isa +++ b/src/arch/arm/isa/insts/str64.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2011-2013,2017,2019 ARM Limited +// Copyright (c) 2011-2013,2017,2019-2020 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -82,6 +82,8 @@ let {{ self.instFlags.extend(["IsMemBarrier", "IsWriteBarrier", "IsReadBarrier"]) + self.memFlags.append("Request::RELEASE") + if self.flavor in ("relex", "exclusive", "exp", "relexp"): self.instFlags.append("IsStoreConditional") self.memFlags.append("Request::LLSC") -- 2.30.2