From acbc03ae464b027fe93dca3a0bc796ef63f53113 Mon Sep 17 00:00:00 2001
From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Mon, 9 Jan 2012 20:13:31 -0600
Subject: [PATCH] X86: Add memory fence to I/O instructions

---
 .../isa/insts/general_purpose/input_output/general_io.py  | 8 ++++++++
 .../isa/insts/general_purpose/input_output/string_io.py   | 8 ++++++++
 2 files changed, 16 insertions(+)

diff --git a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
index c034f8a48..0465b3447 100644
--- a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
+++ b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
@@ -42,26 +42,34 @@ microcode = '''
     def macroop IN_R_I {
         .adjust_imm trimImm(8)
         limm t1, imm, dataSize=asz
+        mfence
         ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \
             nonSpec=True
+        mfence
     };
 
     def macroop IN_R_R {
         zexti t2, regm, 15, dataSize=8
+        mfence
         ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
             nonSpec=True
+        mfence
     };
 
     def macroop OUT_I_R {
         .adjust_imm trimImm(8)
         limm t1, imm, dataSize=8
+        mfence
         st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \
             nonSpec=True
+        mfence
     };
 
     def macroop OUT_R_R {
         zexti t2, reg, 15, dataSize=8
+        mfence
         st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
             nonSpec=True
+        mfence
     };
 '''
diff --git a/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py b/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py
index 3c90ee7e7..044e57edc 100644
--- a/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py
+++ b/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py
@@ -45,9 +45,11 @@ def macroop INS_M_R {
 
     zexti t2, reg, 15, dataSize=8
 
+    mfence
     ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
         nonSpec=True
     st t6, es, [1, t0, rdi]
+    mfence
 
     add rdi, rdi, t3, dataSize=asz
 };
@@ -63,6 +65,7 @@ def macroop INS_E_M_R {
 
     zexti t2, reg, 15, dataSize=8
 
+    mfence
 topOfLoop:
     ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
         nonSpec=True
@@ -72,6 +75,7 @@ topOfLoop:
     add rdi, rdi, t3, dataSize=asz
     br label("topOfLoop"), flags=(nCEZF,)
 end:
+    mfence
     fault "NoFault"
 };
 
@@ -84,9 +88,11 @@ def macroop OUTS_R_M {
 
     zexti t2, reg, 15, dataSize=8
 
+    mfence
     ld t6, ds, [1, t0, rsi]
     st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
         nonSpec=True
+    mfence
 
     add rsi, rsi, t3, dataSize=asz
 };
@@ -102,6 +108,7 @@ def macroop OUTS_E_R_M {
 
     zexti t2, reg, 15, dataSize=8
 
+    mfence
 topOfLoop:
     ld t6, ds, [1, t0, rsi]
     st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
@@ -111,6 +118,7 @@ topOfLoop:
     add rsi, rsi, t3, dataSize=asz
     br label("topOfLoop"), flags=(nCEZF,)
 end:
+    mfence
     fault "NoFault"
 };
 '''
-- 
2.30.2