From acc0d914ca4271d7ac978116dd1ac185ab986c27 Mon Sep 17 00:00:00 2001
From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Fri, 10 Jul 2020 13:03:49 +0200
Subject: [PATCH] Add POR start/end logging in simsoc testbench

---
 gram/simulation/simsoctb.v | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/gram/simulation/simsoctb.v b/gram/simulation/simsoctb.v
index 4c1cabf..9849845 100644
--- a/gram/simulation/simsoctb.v
+++ b/gram/simulation/simsoctb.v
@@ -112,7 +112,9 @@ module simsoctb;
   initial
     begin
       uart_rx <= 1'b1;
+      $display("[%t] Starting POR",$time);
       #700000; // POR is ~700us
+      $display("[%t] POR complete",$time);
 
       // Software control
       wishbone_write(32'h00009000 >> 2, 8'h0E); // DFII_CONTROL_ODT|DFII_CONTROL_RESET_N|DFI_CONTROL_CKE
-- 
2.30.2