From acf26c23f766ef2da5f1a90896d7f7090abe6214 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 14 Mar 2020 10:15:31 +0000 Subject: [PATCH] --- openpower.mdwn | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/openpower.mdwn b/openpower.mdwn index ef453a3d9..4c319dde5 100644 --- a/openpower.mdwn +++ b/openpower.mdwn @@ -49,6 +49,10 @@ the concept is dropped on top of a pre-existing ISA. Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1. When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead. +## Carry + +SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Therefore, an extra SPR will be required which allows context switches to save this full set of carry bits. + # Integer Overflow / Saturate Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE). To be done instead as CSRs / vector-flags on *standard* arithmetic operations. -- 2.30.2