From acfb233685a69078ef9c04829815436b687beae8 Mon Sep 17 00:00:00 2001 From: Cui Jin Date: Tue, 22 Dec 2020 16:46:46 +0800 Subject: [PATCH] arch-riscv: fix MIE csr register setting bugs Any changes on xIE bits changes should trigger the updating of CSR register. The old condition is wrongly reversed. The fix is verified in FS. Jira Issue: https://gem5.atlassian.net/browse/GEM5-855 Change-Id: Ia2c6d3fbfd24d7f9d23f7cfa6f25f893544f4157 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38578 Reviewed-by: Jason Lowe-Power Reviewed-by: Ayaz Akram Maintainer: Jason Lowe-Power Tested-by: kokoro --- src/arch/riscv/isa/formats/standard.isa | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa index 72f7dc1d2..b95af7623 100644 --- a/src/arch/riscv/isa/formats/standard.isa +++ b/src/arch/riscv/isa/formats/standard.isa @@ -383,9 +383,9 @@ def template CSRExecute {{ xc->setMiscReg(MISCREG_FRM, bits(data, 7, 5)); break; case CSR_MIP: case CSR_MIE: - if (oldinterrupt.mei == newinterrupt.mei && - oldinterrupt.mti == newinterrupt.mti && - oldinterrupt.msi == newinterrupt.msi) { + if (oldinterrupt.mei != newinterrupt.mei || + oldinterrupt.mti != newinterrupt.mti || + oldinterrupt.msi != newinterrupt.msi) { xc->setMiscReg(CSRData.at(csr).physIndex,data); } else { std::string error = "Interrupt m bits are " -- 2.30.2