From ad05f87b4a6ab72f6fe3bd37ac5cea017f896aa9 Mon Sep 17 00:00:00 2001 From: Sameera Deshpande Date: Fri, 20 Jul 2012 22:42:03 +0530 Subject: [PATCH] arm.c (arm_cortex_a15_tune): New tune. gcc/ 2012-07-20 Sameera Deshpande Greta Yorsh * config/arm/arm.c (arm_cortex_a15_tune): New tune. * config/arm/arm-cores.def (cortex-a15): Use it. Co-Authored-By: Greta Yorsh From-SVN: r189723 --- gcc/ChangeLog | 6 ++++++ gcc/config/arm/arm-cores.def | 2 +- gcc/config/arm/arm.c | 12 ++++++++++++ 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ca0526819d7..8de3f97b177 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2012-07-20 Sameera Deshpande + Greta Yorsh + + * config/arm/arm.c (arm_cortex_a15_tune): New tune. + * config/arm/arm-cores.def (cortex-a15): Use it. + 2012-07-20 Sameera Deshpande Greta Yorsh diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index 223e41f4fbc..9eb42628693 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -129,7 +129,7 @@ ARM_CORE("cortex-a5", cortexa5, 7A, FL_LDSCHED, cortex_a5) ARM_CORE("cortex-a7", cortexa7, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex) ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, cortex) ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, cortex_a9) -ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex) +ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15) ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, cortex) ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, cortex) ARM_CORE("cortex-r5", cortexr5, 7R, FL_LDSCHED | FL_ARM_DIV, cortex) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index d463caf5cbc..d5316fef641 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -955,6 +955,18 @@ const struct tune_params arm_cortex_tune = false /* Prefer LDRD/STRD. */ }; +const struct tune_params arm_cortex_a15_tune = +{ + arm_9e_rtx_costs, + NULL, + 1, /* Constant limit. */ + 5, /* Max cond insns. */ + ARM_PREFETCH_NOT_BENEFICIAL, + false, /* Prefer constant pool. */ + arm_default_branch_cost, + true /* Prefer LDRD/STRD. */ +}; + /* Branches can be dual-issued on Cortex-A5, so conditional execution is less appealing. Set max_insns_skipped to a low value. */ -- 2.30.2