From ad14cd097e58f8d73b53c13c36bdbe3299f249ad Mon Sep 17 00:00:00 2001
From: Harry Ho <hh@m-labs.hk>
Date: Wed, 8 Jan 2020 14:39:43 +0800
Subject: [PATCH] wishbone: optimise SRAM addr_width

---
 nmigen_soc/wishbone/sram.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/nmigen_soc/wishbone/sram.py b/nmigen_soc/wishbone/sram.py
index 3ee165e..b72687d 100644
--- a/nmigen_soc/wishbone/sram.py
+++ b/nmigen_soc/wishbone/sram.py
@@ -25,7 +25,7 @@ class SRAM(Elaboratable):
         if not read_only:
             self._memdepth += self.memory.depth
         if bus is None:
-            bus = Interface(addr_width=bits_for(self._memdepth),
+            bus = Interface(addr_width=max(0, log2_int(self._memdepth, need_pow2=False)),
                             data_width=self.memory.width,
                             granularity=granularity,
                             features=features,
-- 
2.30.2