From ad2452389edbdc582d173592e7ea7d9e9b5a7b76 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 14 Aug 2019 06:01:42 +0100 Subject: [PATCH] add associated links --- simple_v_extension/abridged_spec.mdwn | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/simple_v_extension/abridged_spec.mdwn b/simple_v_extension/abridged_spec.mdwn index 350548c30..0990d0d0d 100644 --- a/simple_v_extension/abridged_spec.mdwn +++ b/simple_v_extension/abridged_spec.mdwn @@ -41,12 +41,18 @@ and Register or Predicate over-ride tables may be empty: under such circumstances the behaviour becomes effectively identical to standard RV execution, however SV is never truly actually "off". -Note: **there are *no* new opcodes**. The scheme works *entirely* +Note: **there are *no* new vector opcodes**. The scheme works *entirely* on hidden context that augments (nests) *scalar* RISC-V instructions. Thus it may cover existing, future and custom scalar extensions, turning all existing, all future and all custom scalar operations parallel, without requiring any special (identical, parallel variant) opcodes to do so. +Associated proposals for use with 3D and HPC: + +* [[sv.setvl]] - replaces the use of CSRs to set VL (saves 32 bits) +* [[mv.x]] - provides MV.swizzle and MVX (reg[rd] = reg[reg[rs]]) +* [[ztrans_proposal]] - provides trigonometric and transcendental operations + # CSRs There are five CSRs, available in any privilege level: -- 2.30.2