From ad4a21ecaf1d50e133ad21925431b72298f0ef32 Mon Sep 17 00:00:00 2001
From: Shriya Sharma <shriya@redsemiconductor.com>
Date: Tue, 26 Sep 2023 11:22:11 +0100
Subject: [PATCH] Added english language description, spaces and brackets for
 lhzx instruction

---
 openpower/isa/fixedload.mdwn | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 8ab40cb3..d1b69765 100644
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -156,6 +156,12 @@ Pseudo-code:
     EA <- b + (RB)
     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
 
+Description:
+
+    Let the effective address (EA) be the sum
+    (RA|0)+ (RB). The halfword in storage addressed by
+    EA is loaded into RT 48:63. RT 0:47 are set to 0.
+
 Special Registers Altered:
 
     None
-- 
2.30.2